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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. Interface Signals Description
7. Configuration Registers Description
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5
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5.6. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
Byte Offset | Block |
---|---|
0x00_0000 | Reserved |
0x01_0000 | Reserved |
Channel 0 | |
0x02_0000 | Reserved |
0x02_4000 | PHY |
0x02_6000 | Reserved |
0x02_8000 | MAC |
Channel 1 | |
0x03_0000 | Reserved |
0x03_4000 | PHY |
0x03_6000 | Reserved |
0x03_8000 | MAC |
Traffic Controller | |
0x10_0000 | Traffic Controller |
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