Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 6. Interface Signals Description 7. Configuration Registers Description 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling the Design Example
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signals 2.6. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Interface Signals 3.6. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Interface Signals 4.6. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Interface Signals 5.6. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
6. Interface Signals Description x
6.1. Clock and Reset Interface Signals 6.2. Avalon® Memory-Mapped Interface Signals 6.3. Avalon® Streaming Interface Signals 6.4. PHY Interface Signals 6.5. Status Interface 6.6. IEEE 1588v2 Timestamp Interface Signals
7. Configuration Registers Description x
7.1. Register Access Definition 7.2. Low Latency Ethernet 10G MAC 7.3. PHY
7.3. PHY x
7.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. Interface Signals Description
7. Configuration Registers Description
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5

6.1. Clock and Reset Interface Signals

Table 12.  Clock and Reset Interface Signals
Signal Direction Width Description
csr_clk In 1 125 MHz configuration clock for the Avalon® memory-mapped interface and core logic.
i_tx_rst_n In 1 Active-low reset signal for the TX datapath.
i_rx_rst_n In 1 Active-low reset signal for the RX datapath.
mac_clk In 1 156.25 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk.

mac64b_clk

mac32b_clk

Out 1 156.25 MHz and 312.5 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk.

refclk_lg2p5g_p

In 1 156.25 MHz reference clock for PHY.
refclk_10g In 1 156.25 MHz reference clock for the System PLL.
rx_pma_clkout Out 1 CDR recovered clock.
reset 1 In 1 Assert this asynchronous and active-high signal to reset the whole design example.
reset In 1 Assert this asynchronous and active-high signal to reset the MAC and PHY soft IP datapath.
i_system_clk In 1 156.25 MHz reference clock for System PLL.
tx_digitalreset In [NUM_CHANNELS]

Asynchronous and active-high signal to reset MAC and PCS TX portion of the transceiver PHY.
rx_digitalreset In [NUM_CHANNELS]

Asynchronous and active-high signal to reset MAC and PCS RX portion of the transceiver PHY.
tx_digitalreset 1 Out [NUM_CHANNELS] Asynchronous and active-high signal to reset the MAC and PCS TX portion of of the transceiver PHY.
rx_digitalreset 1 Out [NUM_CHANNELS] Asynchronous and active-high signal to reset the MAC and PCS RX portion of of the transceiver PHY.
reconfig_reset In 1 Active-high reset signal for Avalon® memory-mapped interface.
i_rst_n In 1 Active-low global reset asynchronous signal. Do not deassert until the o_rst_ack_n assert.
i_rst_n 1 In 1 Active-low reset asynchronous signal.
mrphy_pll_clkout Out [NUM_CHANNELS] Output clock for 1G/2.5G/5G/10G Multirate Ethernet PHY IP. It provides 156.25 MHz timing reference for 2.5G, 62.5 MHz for 1G, 10M, and 100M.
1 Applicable for USXGMII Design Example.
Level Two Title