Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 6. Interface Signals Description 7. Configuration Registers Description 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling the Design Example
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signals 2.6. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Interface Signals 3.6. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Interface Signals 4.6. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Interface Signals 5.6. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
6. Interface Signals Description x
6.1. Clock and Reset Interface Signals 6.2. Avalon® Memory-Mapped Interface Signals 6.3. Avalon® Streaming Interface Signals 6.4. PHY Interface Signals 6.5. Status Interface 6.6. IEEE 1588v2 Timestamp Interface Signals
7. Configuration Registers Description x
7.1. Register Access Definition 7.2. Low Latency Ethernet 10G MAC 7.3. PHY
7.3. PHY x
7.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. Interface Signals Description
7. Configuration Registers Description
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5

1.2.1. Procedure

You can generate the design example from the IP Parameter Editor.
Figure 3. Example Design Tab
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
  2. Select Agilex™ 5 device family and select a device for your design.
  3. Click Finish to close the wizard.
  4. Select Tools > IP Catalog to open the IP Catalog and select Low Latency Ethernet 10G MAC Intel® FPGA IP .
    The IP parameter editor appears.
  5. Specify a top-level name, the folder for your custom IP variation, and the target device. Click OK.
  6. To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The parameter editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab.
  7. Specify the parameters in the Example Design tab.
  8. Click the Generate Example Design.
The software generates all design files in sub-directories. You require these files to run simulation and compilation.
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