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1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Retrieving SEU Statistic using Mailbox Command
4. Secure Device Manager ECC and SmartVID Errors Detection
5. Agilex™ 5 SEU Mitigation Implementation Guides
6. IP and Software References
7. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
5.6.1. Launching and Setting Up the Fault Injection Debugger
5.6.2. Configuring Your Device using a Software Object File (.sof)
5.6.3. Constraining Regions for Fault Injection
5.6.4. Injecting Errors to Predefined Safe Locations
5.6.5. Blowing Fuse Bit to Enable Injecting All Error Types
5.6.6. Injecting Errors to Random Locations
5.6.7. Injecting Errors to Specific Locations
5.6.8. Injecting Double Adjacent Errors
5.6.9. Injecting SDM ECC Errors
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1.2. Configuration RAM
FPGAs use memory in user logic (bulk memory and registers) and in configuration RAM (CRAM). You can use the Quartus® Prime Programmer to load the CRAM with your design (.sof file). During device configuration, the CRAM configures all FPGA logic and routing.
If an SEU strikes a CRAM bit that is not in use, the effect can be harmless. However, if the affected CRAM bit is in use for critical internal signal routing or lookup table logic bits, the device may experience a functional error.
For more information about CRAM and user design in Agilex™ 5 devices, refer to Agilex™ 5 Configuration User Guide.
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