F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

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ID 792946
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support
3. Getting Started x
3.1. Installing and Licensing Intel FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel FPGA IP 3.5.3. Placement Settings for the 100G Ethernet Intel FPGA IP Core
5. Functional Description x
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description x
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath 5.1.2. 100 GbE TX PCS 5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 100 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

7.1. TX MAC Interface to User Logic

The TX MAC provides an Avalon® streaming interface to the FPGA fabric. The minimum packet size is nine bytes.
Table 8.   Avalon® Streaming TX DatapathAll interface signals are clocked by the clk_txmac clock. The value you specify for Ready Latency in the F-Tile Low Latency 100G Ethernet Intel® FPGA IP parameter editor is the Avalon® streaming readyLatency value on this interface.
Signal Direction Description
clk_txmac Output Clock for the TX logic. Derived from o_clk_tx_div and is an output from the F-Tile Low Latency 100G Ethernet Intel® FPGA IP core. clk_txmac is guaranteed to be stable when tx_lanes_stable is asserted. The frequency of this clock is 390.625 MHz. All TX MAC interface signals are synchronous to clk_txmac .
l8_tx_data[511:0] Input

Data input to MAC. Bit 511 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order.

The F-Tile Low Latency 100G Ethernet Intel® FPGA IP core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

You must send each TX data packet without intermediate idle cycles. Therefore, you must ensure your application can provide the data for a single packet in consecutive clock cycles. If data might not be available otherwise, you must buffer the data in your design and wait to assert l8_tx_startofpacket when you are assured the packet data to send on l8_tx_data[511:0] is available or will be available on time.

If readyLatency = 0, ensure that no data transition at the l8_tx_data bus at the same clock cycle l8_tx_ready is deasserted. You can transition the data at the l8_tx_data bus at the same clock cycle l8_tx_ready is asserted.

If readyLatency = 3, ensure that no data transition at the l8_tx_data bus at the third clock cycle after l8_tx_ready is deasserted. You can transition the data at the l8_tx_data bus at the third clock cycles after l8_tx_ready is asserted.

l8_tx_valid Input When asserted, indicates valid data is available on l8_tx_data[511:0]. You must assert this signal continuously between the assertions of l8_tx_startofpacket and l8_tx_endofpacket for the same packet regardless of the l8_tx_ready status.
l8_tx_startofpacket Input When asserted, indicates the first byte of a frame. When l8_tx_startofpacket is asserted, the MSB of l8_tx_data drives the start of packet.

Packets that drive l8_tx_startofpacket and l8_tx_endofpacket in the same cycle are ignored.

l8_tx_endofpacket Input When asserted, indicates the end of a packet.

Packets that drive l8_tx_startofpacket and l8_tx_endofpacket in the same cycle are ignored.

l8_tx_empty[3:0] Input Specifies the number of empty bytes on l8_tx_data when l8_tx_endofpacket is asserted.
l8_tx_error Input

When asserted in the same cycle as l8_tx_endofpacket, indicates the current packet should be treated as an error packet. Assertion at any other position in the packet is ignored.

The TX statistics counters do not reflect errors the IP core creates in response to this signal.

l8_tx_ready Output When asserted, indicates that the MAC can accept the data. When the readyLatency = 0, the IP core accepts valid data in the same clock cycle in which it asserts l8_tx_ready. When the readyLatency = 3, the IP core accepts valid data 3 clock cycles after it asserts l8_tx_ready.
l8_txstatus_valid Output When asserted, indicates that l8_txstatus_data[39:0] is driving valid data.
l8_txstatus_data[39:0] Output

Specifies information about the transmit frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
l8_txstatus_error[6:0] Output Specifies the error type in the transmit frame. The following fields are defined:
  • Bits[6:3]: Reserved
  • Bit[2]: Payload length error
  • Bit[1]: Oversized frame
  • Bit[0]: Reserved
Figure 19. Client to 100G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface
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