F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

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ID 792946
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support
3. Getting Started x
3.1. Installing and Licensing Intel FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel FPGA IP 3.5.3. Placement Settings for the 100G Ethernet Intel FPGA IP Core
5. Functional Description x
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description x
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath 5.1.2. 100 GbE TX PCS 5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 100 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

5.1.6. Flow Control

Flow control reduces congestion at the local or remote link partner. When either link partner experiences congestion, the respective transmit control sends pause frames. XOFF Pause frames stop the remote transmitter. XON Pause frames let the remote transmitter resume data transmission. The 100G Ethernet Intel FPGA IP core supports both standard and Priority-based Flow Control (PFC) control frames.
Figure 14. Flow Control Module Conceptual OverviewThe flow control module acts as a buffer between client logic and the TX and RX MAC.

Standard Flow Control (Pause Frame Flow Control):
  • Inhibits the next client frame transmission on the reception of a valid Pause frame.
Priority-based Flow Control (PFC):
  • PFC frame transmission follows a priority-based arbitration scheme, where the Frame Type indication is provided for the usage of external downstream logic.
  • Inhibits the per queue client frame transmission on the reception of a valid PFC frame from the client. Includes per-queue PFC Pause quanta duration indicator
Flow Control includes the following features:
Feature Standard Flow Control Priority-based Flow Control (PFC)
Generation and Transmission
Programmable 1-bit or 2-bit XON/XOFF request mode Supported Supported
In 2-bit request mode, programmable selection of register or signal-based control Supported Supported
Programmable destination and source addresses Supported Supported
Programmable pause quanta Supported Supported
Programmable per-queue XOFF frame separation — Supported
Reception and Decode
Programmable destination address for filtering incoming pause and PFC frames Supported Supported
Configurable enable, directing the IP core to ignore incoming flow control frames Supported Supported
Per-queue client frame transmission pause duration indicator — Supported
CAUTION:
The 100G Ethernet Intel FPGA IP core supports the flow control feature for either value of the Ready Latency parameter. However, in standard flow control you might experience data delay if you select the value of 3 for this parameter. The IP core might still hold user data packet in its internal buffer if transmission of the IP core stops due to flow control. This issue does not occur in priority-based flow control.

Section Content
TX Pause/PFC Flow Control Frame Transmission Request
XON/XOFF Pause Frames

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