AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.8. Flow Control Credit Handling

The IP implements credit handling by providing TX and RX flow control credit interfaces to/from the application logic. Each header type (P,NP,CPL) and data type (P,NP,CPL) has independent credit handling. The credits are advertised as limit values as per the PCIe specification. One data credit consists of 16 bytes. One header credit includes the TLP Header, 1DW prefix (if present) and the digest (if present). The credit interfaces on the IP for TX and RX are not time division multiplexed. The initial buffer space for P, NP, CPL header and data is communicated on the first set of clock cycles with a valid assertion. Every time there is an update to credits for a particular type, the credit interface updates the value for that particular type with a valid assertion. A value of 0 credits initially indicates infinite credits.