1.1. Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP v2.0.1
Quartus® Prime Version | Description | Impact |
---|---|---|
24.2 | Verified in the Quartus® Prime software v24.2. | Provides memory subsystem IP for use with Agilex™ 7 F-Series and I-Series FPGAs. |
Note: This documentation is preliminary and subject to change.