AN 1002: Sharing Platform Designer Packaged Subsystems

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ID 786899
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Packaged Subsystems Overview 4. Packaged Subsystem Author Flow 5. Packaged Subsystem User Flow 6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems
2. About This Application Note x
2.1. Document Prerequisites
3. Packaged Subsystems Overview x
3.1. User Personas for Packaged Subsystems 3.2. Terminology for Packaged Subsystems
4. Packaged Subsystem Author Flow x
4.1. Step 1: Create a Project and Platform Designer System 4.2. Step 2: Add Components to the System 4.3. Step 3: Connect Components in the System 4.4. Step 4: Create and Configure a Packaged Subsystem 4.5. Step 5: Revise a Packaged Subsystem
4.4. Step 4: Create and Configure a Packaged Subsystem x
4.4.1. Editing the Packaged Subsystem 4.4.2. Step 4a: Add Two Checkbox Controls 4.4.3. Step 4b: Enable or Disable Modules and Checkboxes 4.4.4. Step 4c: Run run_system_script 4.4.5. Step 4d: Iterate Over All Parameters 4.4.6. Step 4e: Setting DisplayPort IP Functionality 4.4.7. Step 4f: Make Packaged Subsystem Unlockable 4.4.8. Step 4g: Sync System Infos, Assign Base Addresses, and Save
5. Packaged Subsystem User Flow x
5.1. Step 1: Create the User Project and System 5.2. Step 2: Add Components to the User System 5.3. Step 3: Instantiate the Packaged Subsystem 5.4. Step 4: Unlock the Packaged Subsystem 5.5. Step 5: Integrate the Top Hierarchy of the System 5.6. Step 6: Generate HDL and Run Synthesis
1. Answers to Top FAQs
2. About This Application Note
3. Packaged Subsystems Overview
4. Packaged Subsystem Author Flow
5. Packaged Subsystem User Flow
6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems

5.6. Step 6: Generate HDL and Run Synthesis

After completing all system changes, follow these steps to save the system and generate HDL for the system.
  1. In Platform Designer, click File > Save and save any system changes.
  2. To generate the HDL for the system, click the Generate HDL button. If during system generation you encounter any errors regarding source file inconsistencies, right-click the instance in the System View, and then click Edit Component Instantiation to ensure that the file hierarchy includes the correct source files.
  3. When HDL generation is complete, close Platform Designer. The generated HDL files for the user_system appear in the Intel Quartus Prime Project Navigator Files tab as part of the project automatically.
    Figure 33. Files Tab in Project Navigator


  4. To synthesize the design, double-click Synthesis on the Compilation Dashboard.
  5. When synthesis is complete, view the hierarchy for the project in the Hierarchy tab of the Project Navigator.
    Figure 34. Project Navigator Hierarchy Tab Shows Project Hierarchy
Level Two Title