AN 1002: Sharing Platform Designer Packaged Subsystems

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ID 786899
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Packaged Subsystems Overview 4. Packaged Subsystem Author Flow 5. Packaged Subsystem User Flow 6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems
2. About This Application Note x
2.1. Document Prerequisites
3. Packaged Subsystems Overview x
3.1. User Personas for Packaged Subsystems 3.2. Terminology for Packaged Subsystems
4. Packaged Subsystem Author Flow x
4.1. Step 1: Create a Project and Platform Designer System 4.2. Step 2: Add Components to the System 4.3. Step 3: Connect Components in the System 4.4. Step 4: Create and Configure a Packaged Subsystem 4.5. Step 5: Revise a Packaged Subsystem
4.4. Step 4: Create and Configure a Packaged Subsystem x
4.4.1. Editing the Packaged Subsystem 4.4.2. Step 4a: Add Two Checkbox Controls 4.4.3. Step 4b: Enable or Disable Modules and Checkboxes 4.4.4. Step 4c: Run run_system_script 4.4.5. Step 4d: Iterate Over All Parameters 4.4.6. Step 4e: Setting DisplayPort IP Functionality 4.4.7. Step 4f: Make Packaged Subsystem Unlockable 4.4.8. Step 4g: Sync System Infos, Assign Base Addresses, and Save
5. Packaged Subsystem User Flow x
5.1. Step 1: Create the User Project and System 5.2. Step 2: Add Components to the User System 5.3. Step 3: Instantiate the Packaged Subsystem 5.4. Step 4: Unlock the Packaged Subsystem 5.5. Step 5: Integrate the Top Hierarchy of the System 5.6. Step 6: Generate HDL and Run Synthesis
1. Answers to Top FAQs
2. About This Application Note
3. Packaged Subsystems Overview
4. Packaged Subsystem Author Flow
5. Packaged Subsystem User Flow
6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems

4.3. Step 3: Connect Components in the System

The Connections column in the System View tab displays the potential connection points between components, represented as a connection dot between connecting wires. A filled dot shows that a connection is made; an open dot shows an unconnected connection point. Clicking the connection dot toggles the connection status. Follow these steps to implement the connections for the system.

  1. Click inside the open connection dot to enable the connection between the out_interface of the reset_bridge and the reset input of all other components. When you make a connection, Platform Designer changes the connection line to black, and fills the connection dot. Clicking a filled-in dot removes the connection.
    Figure 10. Potential and Implemented Connection


  2. Repeat step 1 to specify the following component connections:
    Table 3.  Subsystem Component Connections
    Module Name Interface Connect To
    dp_mgmt_clk out_clk

    dp.clk

    dp.xcvr_mgmt_clk

    dp.clk_cal

    dp_rx_mgmt_bridge.clk

    pio_0.clk

    pio_1.clk
    clk_16 out_clk dp.aux_clk
    dp_mgmt_bridge m0

    pio_0.s1

    pio_1.s1
  3. To export an interface, double-click in the component's Export column, and retain the default name for the exported interface. Export the following interfaces:
    • Clock inputs and reset inputs: tx_vid_clk and rx_vid_clk
    • dp_mgmt_bridge.s0 and pio_0 and pio_1 external connections
  4. Click the Sync System Infos button. At this point you can safely ignore any clock warnings.
  5. If Platform Designer indicates that there are addressing errors, click System > Assign Base Addresses.
  6. To save the Platform Designer system changes, click File > Save.
  7. To generate the HDL for the subsystem, click the Generate HDL button.
Level Two Title