AN 1002: Sharing Platform Designer Packaged Subsystems

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ID 786899
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Packaged Subsystems Overview 4. Packaged Subsystem Author Flow 5. Packaged Subsystem User Flow 6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems
2. About This Application Note x
2.1. Document Prerequisites
3. Packaged Subsystems Overview x
3.1. User Personas for Packaged Subsystems 3.2. Terminology for Packaged Subsystems
4. Packaged Subsystem Author Flow x
4.1. Step 1: Create a Project and Platform Designer System 4.2. Step 2: Add Components to the System 4.3. Step 3: Connect Components in the System 4.4. Step 4: Create and Configure a Packaged Subsystem 4.5. Step 5: Revise a Packaged Subsystem
4.4. Step 4: Create and Configure a Packaged Subsystem x
4.4.1. Editing the Packaged Subsystem 4.4.2. Step 4a: Add Two Checkbox Controls 4.4.3. Step 4b: Enable or Disable Modules and Checkboxes 4.4.4. Step 4c: Run run_system_script 4.4.5. Step 4d: Iterate Over All Parameters 4.4.6. Step 4e: Setting DisplayPort IP Functionality 4.4.7. Step 4f: Make Packaged Subsystem Unlockable 4.4.8. Step 4g: Sync System Infos, Assign Base Addresses, and Save
5. Packaged Subsystem User Flow x
5.1. Step 1: Create the User Project and System 5.2. Step 2: Add Components to the User System 5.3. Step 3: Instantiate the Packaged Subsystem 5.4. Step 4: Unlock the Packaged Subsystem 5.5. Step 5: Integrate the Top Hierarchy of the System 5.6. Step 6: Generate HDL and Run Synthesis
1. Answers to Top FAQs
2. About This Application Note
3. Packaged Subsystems Overview
4. Packaged Subsystem Author Flow
5. Packaged Subsystem User Flow
6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems

5.5. Step 5: Integrate the Top Hierarchy of the System

Follow these steps to integrate the top hierarchy of the system.
  1. Implement the following system connections to integrate the top hierarchy:
    Table 5.  Top Hierarchy Integration System Connections
    Module Name Interface Connect To
    cpu_reset_bridge out_reset
    • onchip_mem.reset1
    • jtag_uart.reset
    • sys_clk_timer.reset
    • i2c_master.reset_sink
    • sysid.reset
    • cpu.reset
    mgmt_clk out_clk
    • cpu_reset_bridge.clk
    • onchip_mem.clk1
    • jtag_uart.clk
    • i2c_master.clock
    • sysid.clk
    • cpu.clk
    • dp_rx.dp_mgmt_clk_in_clk
    • dp_tx.dp_mgmt_clk_in_clk
    cpu data_manager
    • onchip_mem.s1
    • jtag_uart.avalon_jtag_slave
    • sys_clock_timer.s1
    • i2c_master.csr
    • sysid.control_slave
    • cpu.timer_sw_agent
    • cpu.dm_agent
    • dp_rx.dp_rx_mgmt_bridge_s0
    • dp_tx.dp_tx_mgmt_bridge_s0
    instruction_manager
    • onchip_mem.s1
    • cpu.dm_agent
    dbg_reset_out
    • onchip_mem.reset1
    • jtag_uart.reset
    • i2c_master.reset_sink
    platform_irq_rx
    • jtag_uart.irq
    • sys_clock_timer.irq
    • i2c_master.interrupt_sender
    • dp_rx.dp_rx_mgmt_interrupt
    • dp_tx.dp_tx_mgmt_interrupt
    dp_rx_clk_16 out_clk dp_rx.clk_16_in_clk
    dp_rx_reset_bridge out_reset dp_rx.reset_bridge_in_reset
    dp_tx_clk_16 out_clk dp_tx.clk_16_in_clk
    dp_tx_reset_bridge out_reset dp_tx.reset_bridge_in_reset
  2. Complete the system by exporting all the interfaces that the system describes as a "conduit," as well as any remaining "unconnected" interfaces.
  3. To assign base addresses, click System > Assign Base Addresses.
  4. To modify the cpu component for compatibility in the new system, select the component to display the component parameters in the Parameters tab.
  5. For the Reset Agent, select onchip_mem.s1.
  6. To clear any system information errors, click the Sync System Infos button.
  7. If Platform Designer reports any address space errors, click System > Assign Base Addresses, and then make any base address assignments.
  8. To view a schematic of the completed system, click View Schematic.
Figure 32. Completed System Schematic View in Platform Designer


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