AN 1002: Sharing Platform Designer Packaged Subsystems

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ID 786899
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Packaged Subsystems Overview 4. Packaged Subsystem Author Flow 5. Packaged Subsystem User Flow 6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems
2. About This Application Note x
2.1. Document Prerequisites
3. Packaged Subsystems Overview x
3.1. User Personas for Packaged Subsystems 3.2. Terminology for Packaged Subsystems
4. Packaged Subsystem Author Flow x
4.1. Step 1: Create a Project and Platform Designer System 4.2. Step 2: Add Components to the System 4.3. Step 3: Connect Components in the System 4.4. Step 4: Create and Configure a Packaged Subsystem 4.5. Step 5: Revise a Packaged Subsystem
4.4. Step 4: Create and Configure a Packaged Subsystem x
4.4.1. Editing the Packaged Subsystem 4.4.2. Step 4a: Add Two Checkbox Controls 4.4.3. Step 4b: Enable or Disable Modules and Checkboxes 4.4.4. Step 4c: Run run_system_script 4.4.5. Step 4d: Iterate Over All Parameters 4.4.6. Step 4e: Setting DisplayPort IP Functionality 4.4.7. Step 4f: Make Packaged Subsystem Unlockable 4.4.8. Step 4g: Sync System Infos, Assign Base Addresses, and Save
5. Packaged Subsystem User Flow x
5.1. Step 1: Create the User Project and System 5.2. Step 2: Add Components to the User System 5.3. Step 3: Instantiate the Packaged Subsystem 5.4. Step 4: Unlock the Packaged Subsystem 5.5. Step 5: Integrate the Top Hierarchy of the System 5.6. Step 6: Generate HDL and Run Synthesis
1. Answers to Top FAQs
2. About This Application Note
3. Packaged Subsystems Overview
4. Packaged Subsystem Author Flow
5. Packaged Subsystem User Flow
6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems

4.2. Step 2: Add Components to the System

After creating the new Platform Designer system, follow these steps to add Intel FPGA IP components from the IP Catalog to the system. You later save this system as a packaged subsystem.

  1. In Platform Designer's IP Catalog, type reset bridge in the Search field and then double-click Reset Bridge Intel FPGA IP. The parameter editor appears.
    Figure 8. Reset Bridge Intel FPGA IP Parameter Editor


  2. Specify the following entity name and parameters for the IP variation:
    • Active low reset—enable this parameter.
    • Synchronous edges—select None.
    • HDL entity name—reset_bridge.
    • Retain defaults for all other parameters and click Finish.
  3. Repeat steps 1 through 2 to add the following components and parameter options to the subsystem. Retain defaults for all other parameters.
    Table 2.  Subsystem IP Parameters and Module Names
    Intel FPGA IP Parameters To Specify HDL Entity Name
    Clock Bridge Intel FPGA IP Explicit clock rate—100000000 Hz dp_mgmt_clk
    Clock Bridge Intel FPGA IP Explicit clock rate—16000000 Hz clk_16
    DisplayPort Intel FPGA IP
    • Support DisplayPort source—disable
    • Support DisplayPort sink—disable
    		dp
    Avalon Memory Mapped Pipeline Bridge Intel FPGA IP Use automatically-determined address width—Enable dp_mgmt_bridge
    PIO (Parallel I/O) Intel FPGA IP
    • Width—1
    • Direction—Input
    		pio_0
    PIO (Parallel I/O) Intel FPGA IP
    • Width—1
    • Direction—Input
    		pio_1
Figure 9. System Components in the System View Tab


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