Intel® Simics® Simulator for Intel® FPGAs: User Guide

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ID 784383
Date 11/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

6.3.2. Temporal Breakpoints

Intel® Simics® simulator can handle temporal breakpoints. This means that you can set up a breakpoint that triggers after some configurable time. Since in Intel® Simics® simulator, the concept of time can be related CPU steps or cycles, the temporal breakpoint can also be referred to a specific step or a cycle count as measured by a given processor.

The Intel® Simics® simulator commands used to set up these breakpoints are the following: 

bp.cycle.break [object]  cycles [-absolute]
bp.step.break  [object]  steps  [-absolute]
bp.time.break  [object]  time   [-absolute]

The above commands configure a breakpoint to trigger after the specified number of cycles, steps, or seconds. The steps and cycles operate over the object provided as an argument that normally corresponds to a CPU. If no object is specified, the currently selected frontend processor is used (see psel command). If the -absolute argument is specified, the cycles, steps, or time is counted from the start of the simulation instead. The following capture shows some examples on how you can use these commands: 

#Intel Simics simulator CLI  
simics> ptime
-------------------------------------------------------------
     Processor                Steps      Cycles      Time (s)
-------------------------------------------------------------
system...agilex_hps.core[0]   306259127  306259209   3.794
-------------------------------------------------------------

simics> bp.cycle.break 1000 
Breakpoint 1: system...agilex_hps.core[0] will break at cycle 306260209 
simics> r 
[bp.cycle] Breakpoint 1: system...agilex_hps.core[0] reached cycle 306260209 
simics> ptime
-------------------------------------------------------------
     Processor                Steps      Cycles      Time (s)
-------------------------------------------------------------
system...agilex_hps.core[0]   306260127  306260209   3.794
-------------------------------------------------------------

simics> bp.step.break 1000 
Breakpoint 2: system...agilex_hps.core[0] will break at step 306261127 
simics> bp.list
------------------------------------------------------------------------------
ID                     Description                    Enabled    Oneshot Hit
                                                                         count 
------------------------------------------------------------------------------
2  system...agilex_hps.core[0] br .. step 306261127   true       true   0 
------------------------------------------------------------------------------

simics> r 
[bp.step] Breakpoint 2: agilex.hps.core[0] reached step 306261127 
simics> ptime
-------------------------------------------------------------
     Processor                Steps      Cycles      Time (s)
-------------------------------------------------------------
system...agilex_hps.core[0]   306261127  306261209   3.794
-------------------------------------------------------------

simics> bp.time.break 0.5 
Breakpoint 3: system...agilex_hps.core[0] will break at time 4.29421449 
simics> r 
[bp.time] Breakpoint 3: system...agilex_hps.core[0] reached time 4.29421449 
simics> ptime
-------------------------------------------------------------
     Processor                Steps      Cycles      Time (s)
-------------------------------------------------------------
system...agilex_hps.core[0]   346261127  346261209   4.294
-------------------------------------------------------------

In the above example, the following exercises are being executed:

  • Initially, the simulation is paused and the ptime command is called to obtain the current CPU selected, the steps, cycles and time. Not that the current number of cycles is 306259209.
  • Then, a temporal breakpoint is configured to trigger after 1000 cycles. As no object is provided as argument, this applies to the core[0] which is the current one selected. The simulation is run.
  • The simulation is stopped as the breakpoint got triggered. Notice that there is a message indicating that the simulation reached cycle 306260209 which is actually the expected cycle number after the 1000 cycles configured for the breakpoint to trigger. This cycle count is also confirmed by calling the ptime command.
  • Next, a new temporal breakpoint is configured to occur after 1000 steps of the current core selected. The breakpoint are listed and you can see that this new breakpoint has the ID equal to 2. The simulation is run.
  • The simulation is stopped as the breakpoint got triggered and you can confirm that this occurred at the expected step number based on the log message that indicates that you reached step 306261127, which corresponds to 1000 steps after the breakpoint was set. This is also confirmed with the ptime command.
  • Next a new temporal breakpoint is configured to trigger after 0.5 seconds. The simulation is run.
  • The simulation is stopped as the breakpoint got triggered and you can confirm that the time in which the trigger occurred is the expected based on the message saying that you reached time 4.29421449, which corresponds to 0.5 seconds after the breakpoint was set. This also is confirmed when calling the ptime command again.
Note: The temporal breakpoints can also be set directly using commands over the object (CPU) selected. The following capture shows how the same commands used in the previous example can be called using the core[0] object: 
#Intel Simics simulator CLI 

simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].bp-break-cycle 1000
Breakpoint 6: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] will break at cycle 346262209
simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].bp-break-step 1000
Breakpoint 7: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] will break at step 346262127
simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].bp-break-time 0.5
Breakpoint 8: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] will break at time 4.79421449
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