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1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
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2.5.1. Test Procedure
After you compile the Triple-Speed Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.
To turn on the System Console and test the hardware design example, follow these steps:
- In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
- In the Tcl Console pane, type cd hwtest/agx/2xtbi_pma to change directory to <design_example_dir>/hardware_test_design/hwtest/agx/2xtbi_pma.
- Type source basic/basic.tcl.
- Type list_jtag to display a list of JTAG master indexes that are connected to your board.
- Type set_jtag<number_of appropriate_JTAG_master> to select the JTAG master.
- Type source hwtest_main.tcl to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message: