F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

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ID 781679
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

1.4. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Agilex™ 7 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf .
  3. On the Processing menu, click Start Compilation.
  4. After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory. Follow these steps to program the hardware design example on the Agilex™ 7 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile) to which your Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
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