F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 781679
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.10.07 24.3 22.4.0 Updated the development kit display name to Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile) in the following topics:
  • Quick Start Guide
  • Generating the Design Example
  • Design Example Parameters
  • Compiling and Configuring the Design Example
  • Hardware and Software Requirements
2024.07.08 24.1 22.3.0 Updated Block Diagram of the 10/100/1000Mb Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver Simulation Testbench.
2023.10.02 23.3 22.1.0
  • Added information on hardware support:
    • Added new topics:
      • Compiling and Configuring the Design Example in Hardware
      • Hardware Testing
      • Interface Signals
    • Updated the following topics:
      • Quick Start Guide
      • Directory Structure
      • Features
      • Hardware and Software Requirements
  • Updated OPN number in the following topics:
    • Generating the Design Example topic.
    • Hardware and Software Requirements topic.
  • Added a new Design Constraints topic.
2023.06.26 23.2 22.0.0 Initial release.
Level Two Title