High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide x
2.1. Creating an Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping Use case 1: 1 × 1 Full Address Connection Use case 2: 16 × 16 Cross Bar Connection 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

3.2.1. Initiator to Target NoC Mapping

This topic describes the configurations of the design example.

Use case 1: 1 × 1 Full Address Connection

In this configuration each pair of initiator and target is directly mapped. As shown in the figure below, the CH0 PC0 channel of the HBM controller connects to target 0 which connects to initiator 0.

Figure 6. 1 × 1 Full Address Connection

The table below illustrates the mapping of HBM2E controller pseudo-channels to HBM2E DRAM channels to targets and HBM2E DRAM channels.

Table 3.  Channel Mapping
HBM2E IP GUI Channel AXI4 Channel (HBMC) HBM2E DRAM Channel
Channel 0 ch0_u0 Channel E
ch0_u1
Channel 1 ch1_u0 Channel F
ch1_u1
Channel 2 ch2_u0 Channel A
ch2_u1
Channel 3 ch3_u0 Channel B
ch3_u1
Channel 4 ch4_u0 Channel G
ch4_u1
Channel 5 ch5_u0 Channel H
ch5_u1
Channel 6 ch6_u0 Channel C
ch6_u1
Channel 7 ch7_u0 Channel D
ch7_u1

Use case 2: 16 × 16 Cross Bar Connection

In this configuration the address map of each initiator is configured to allow it to drive traffic to all of the 16 targets. You can use this design example configuration as a starting point for designs that have multiple masters accessing the same HBM2E pseudo-channels, for example when there is ping-pong buffering.

Note: You cannot choose this configuration if you generate the design example with fewer than 8 channels enabled.

The design example offers options to use the AXI4-Lite access and fabric NoC with each of the NoC connectivity configurations.

Level Two Title