High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project

This topic outlines the flow for simulating the HBM2E IP instantiated in your project, rather than the HBM2E design example.
  1. In your simulation project, include <project_directory>\<IP_name>\sim\<IP_name>.v
  2. The generated HBM2E IP simulation file set does not include an HBM2E memory model file; you must add a memory model file to the project. Intel® recommends that you use the memory model from the design example simulation file set generated from your IP: hbm_fp_0_example_design\sim\ip\ed_sim\ed_sim_hbm_fp_0\hbm_arch_fp_10\sim\altera_hbm2e_model.sv
  3. The HBM2E IP netlist does not include the mapping for the NoC initiators-targets connectivity, and the address mapping. You must add the RTL registration statements in the top-level of your design for simulating your HBM2E IP. You can refer to the registration statements included in the ed_sim.v file generated with the design example.
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