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1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System
2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP
2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation
2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example
2.5. Using the HBM2E Design Example with the Test Engine IP
2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor
2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.8.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation
2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS*
2.8.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE
2.8.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator
2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
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3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
The HBM2E design example demonstrates the basic functions of the IP. The design performs successful read and write requests from user logic to the HBM2E DRAM memory, though the HBM2E IP.
You can specify the parameter settings of your choice and generate the design example from the Example Design tab in the IP parameter editor.