High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

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ID 773264
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Agilex™ 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP 5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Agilex™ 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Agilex™ 7 HBM2E Features 2.4. Agilex™ 7 M-Series HBM2E Controller Features 2.5. Agilex™ 7 M-Series FPGA HBM2E IP Device Family Support
3. Agilex™ 7 M-Series HBM2E Architecture x
3.1. Agilex™ 7 M-Series HBM2E Introduction 3.2. Agilex™ 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Agilex™ 7 M-Series UIB Architecture 3.5. Agilex™ 7 M-Series HBM2E Controller Architecture
3.5. Agilex™ 7 M-Series HBM2E Controller Architecture x
3.5.1. Agilex™ 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.1. Creating an Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. Requirement and Timing of the hbm_reset_n Signal 5.2.3. 'Do not connect' Signals 5.2.4. Asynchronous HBM2E Controller Signals 5.2.5. AXI4 Interface Signals 5.2.6. AXI4-Lite Interface
5.3. User AXI Interface Timing x
Handshake Protocol AXI IDs AXI Ordering 5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers 5.5.5. Error Injection Registers
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface FPGA IP
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Agilex™ 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow

5.3. User AXI Interface Timing

This section explains the interface timing details between user logic and the HBM2E controller via the hard memory NoC. User interface signals follow the AXI4 protocol specification while passing data to and from the HBM2E controller.

The AXI interface consists of the following channels:

  • Write Address channel – Master (user logic or target NoC interface unit) provides relevant signals to issue a write command to the slave (initiator NoC interface unit or HBM2E controller).
  • Write data channel – Master provides the write data signals corresponding to the write address.
  • Write response channel – Slave provides response on the status of the issued write command to the master.
  • Read Address channel – Master provides relevant signals to issue a read command to the slave.
  • Read data channel – Slave provides read data and read data valid signals corresponding to the read command to the master.

All transactions in the five channels use a handshake mechanism for the master and slave to communicate and transfer information.

Handshake Protocol

All five transaction channels use the same VALID/READY handshake process to transfer address, data, and control information. Both the master and slave can control the rate at which information moves between master and slave. The source generates the VALID signal to indicate availability of the address, data, or control information. The destination generates the READY signal to indicate that it can accept the information. Transfer occurs only when both the VALID and READY signals are HIGH.

Figure 17. AXI Protocol Handshake Process

In the figure above, the source presents the address, data or control information after T1 and asserts the VALID signal. The destination asserts the READY signal after T2, and the source must keep its information stable until the transfer occurs at T3, when this assertion occurs. In this example, the source asserts the VALID signal prior to the destination asserting the READY signal. Once the source asserts the VALID signal, it must remain asserted until the handshake occurs, at a rising clock edge at which VALID and READY are both high. Once the destination asserts READY, it can deassert READY before the source asserts VALID. The destination can assert READY whenever it is ready to accept data, or in response to a VALID assertion from the source.

AXI IDs

In an AXI system with multiple masters, the AXI IDs used for the ordering model include the infrastructure IDs that identify each master uniquely. The ordering model applies independently to each master in the system.

The AXI ordering model also requires that all transactions with the same ID in the same direction must provide their responses in the order in which they are issued. Because the read and write address channels are independent, if an ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transaction before issuing the second transaction. If a master issues a transaction in one direction before it has received a response to an earlier transaction in the opposite direction, there is no ordering guarantee between the two transactions. An AXI master can also issue several transactions with different IDs, indicating that the HBM controller can re-order these transactions. This usually enables the HBM controller to make more efficient accesses to the memory device.

AXI4-Lite transactions have no associated ID and are always handled in order.

AXI Ordering

The AXI system imposes no ordering restrictions between read and write transactions. Read and write can complete in any order, even if the read address AXI ID (ARID) of a read transaction is the same as the write address AXI ID (AWID) of a write transaction. If a master requires a given relationship between a read transaction and a write transaction, it must ensure that the earlier transaction is completed before it issues a subsequent transaction. A master can consider the earlier transaction complete only when one of the following is true:

  • For a read transaction, it receives the last of the read data.
  • For a write transaction, it receives the write response.

Section Content
AXI Write Transaction
AXI Read Transaction

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