High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

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ID 773264
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Agilex™ 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP 5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Agilex™ 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Agilex™ 7 HBM2E Features 2.4. Agilex™ 7 M-Series HBM2E Controller Features 2.5. Agilex™ 7 M-Series FPGA HBM2E IP Device Family Support
3. Agilex™ 7 M-Series HBM2E Architecture x
3.1. Agilex™ 7 M-Series HBM2E Introduction 3.2. Agilex™ 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Agilex™ 7 M-Series UIB Architecture 3.5. Agilex™ 7 M-Series HBM2E Controller Architecture
3.5. Agilex™ 7 M-Series HBM2E Controller Architecture x
3.5.1. Agilex™ 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.1. Creating an Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. Requirement and Timing of the hbm_reset_n Signal 5.2.3. 'Do not connect' Signals 5.2.4. Asynchronous HBM2E Controller Signals 5.2.5. AXI4 Interface Signals 5.2.6. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers 5.5.5. Error Injection Registers
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface FPGA IP
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Agilex™ 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow

A.2. Simulating HBM2E User Designs

To run the simulations with your HBM2E designs created using the Quartus® Prime software flow, you must manually add the RTL simulation registration include file (.inc) in the top-level of your design. The initiator-to-target connectivity and address mapping are not included in the netlist. If you use the Platform Designer flow to make connection between initiators and targets and generate a design, it creates the registration file (.inc) for your design. In this case, you do not need to manually add the registrations statements in the top-level of your design.
You must add one registration statement for each initiator-to-target connection, specifying the start address and the size of that connection’s address range. Refer to the Simulating the NoC Designs section in the Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide for detailed information on how to add NoC connectivity and address mapping to the simulation net list.

The HBM2E FPGA IP design example creates simulation files with registration statements. You can refer to the registration statements included in the ed_sim.v file generated with the design example. The ed_sim.v file resides at this location: <your_directory>/hbm_fp_0_example_design/sim/ed_sim/sim/ed_sim.v

The following code fragment shows a snapshot of the registration statements for a single-channel design:

.noc_initiator_b256.iniu_0.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_u0.target_0.target_inst_0.get_if() , 0, 31'h40000000);
.noc_initiator_b256.iniu_1.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_u1.target_0.target_inst_0.get_if() , 0, 31'h40000000);
.noc_initiator_b256.iniu_0.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_ch1_sb.target_0.target_lite_inst_0.target_inst_0.get_if() , 44'h40000000, 31'h8000000);
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