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1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Agilex™ 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow
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A.2. Simulating HBM2E User Designs
To run the simulations with your HBM2E designs created using the Quartus® Prime software flow, you must manually add the RTL simulation registration include file (.inc) in the top-level of your design. The initiator-to-target connectivity and address mapping are not included in the netlist. If you use the Platform Designer flow to make connection between initiators and targets and generate a design, it creates the registration file (.inc) for your design. In this case, you do not need to manually add the registrations statements in the top-level of your design.
You must add one registration statement for each initiator-to-target connection, specifying the start address and the size of that connection’s address range. Refer to the Simulating the NoC Designs section in the Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide for detailed information on how to add NoC connectivity and address mapping to the simulation net list.
The HBM2E FPGA IP design example creates simulation files with registration statements. You can refer to the registration statements included in the ed_sim.v file generated with the design example. The ed_sim.v file resides at this location: <your_directory>/hbm_fp_0_example_design/sim/ed_sim/sim/ed_sim.v
The following code fragment shows a snapshot of the registration statements for a single-channel design:
.noc_initiator_b256.iniu_0.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_u0.target_0.target_inst_0.get_if() , 0, 31'h40000000); .noc_initiator_b256.iniu_1.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_u1.target_0.target_inst_0.get_if() , 0, 31'h40000000); .noc_initiator_b256.iniu_0.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_ch1_sb.target_0.target_lite_inst_0.target_inst_0.get_if() , 44'h40000000, 31'h8000000);