External Memory Interfaces Agilex™ 7 M-Series FPGA IP Core Release Notes

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ID 772635
Date 11/18/2024
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1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes
1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes x
1.1. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v1.0.0 1.2. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.2.0 1.3. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.1.0 1.4. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.0.0 1.5. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v5.0.0 1.6. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v4.0.0 1.7. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v3.0.0
1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes

1.1. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v1.0.0

Table 1.  v1.0.0 2024.11.18
Description Impact
External Memory Interface IP for Agilex™ 7 M-Series devices is now divided into individual IPs based on memory protocol and format.

This release provides separate IPs for DDR4 Component, DDR4 DIMM, DDR5 Component, DDR5 DIMM, and LPDDR5. Each IP is now labeled as version 1.0.0.

Verified in the Quartus® Prime software v24.3. Provides external memory interface IP for DDR4, DDR5, and LPDDR5 external memory for Agilex™ 7 M-Series devices. The tables that follow summarize speed and feature support.
Table 2.   Agilex™ 7 M-Series Fabric EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Component 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
UDIMM 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
SODIMM 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
RDIMM 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
DDR5 Memory Format Component 5600/2200 (1R) 2 5600/2200 (1R) 2 5600/2200 (1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (2R) 2 4400/2200 (2R) 2 4400/2200 (2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
UDIMM 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
SODIMM 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
RDIMM 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
LPDDR5 Memory Format Component 5500/2200 (1R) 2 5500/2200 (1R) 2 5500/2200 (1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
3200/1600 (2R) 2 3200/1600 (2R) 2 3200/1600 (2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS and QuestaSim.
  • 2 = Current performance in the Quartus® Prime software. Check the External Memory Interface Spec Estimator for production performance.
  • 3 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 3.   Agilex™ 7 M-Series Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
SODIMM, UDIMM 2 X X X X  
RDIMM 2 X X X X  
Controller Hard controller X X X X X
3DS 3DS          
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
NoC X X X X X
Debug EMIF Toolkit 3 X X X X X
Simulation Abstract PHY          
Simulators 1 VCS 4 X X      
VCS-MX 4 X X      
ModelSim SE 4 X X      
Xcelium          
Aldec          
DDR5 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
SODIMM, UDIMM X X X X X
RDIMM X X X X  
Controller Hard controller X X X X X
3DS 3DS          
Design Example   X X X X X
DM DM pins X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
NoC X X X X X
Debug EMIF toolkit 3 X X X X X
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
LPDDR5 Interface Width 32 X X X X X
16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DM DM pins X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
NoC X X X X X
Debug EMIF toolkit 3 X X X X X
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
  • 2 = Only supported in fabric sync AXI access mode.
  • 3 = VREF OUT margining tab only reports results for Rank 0. Rank 1 is not reported.
  • 4 = DDR4 DIMM configurations do not finish the simulation.
  • Note: Address mirroring is handled by the controller when needed.
    .
Table 4.   Intel Agilex® 7 M-Series HPS EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Component 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X 1 X X 3   X 1 X X 3   X 1 X X 3  
DDR5 Memory Format Component 5600/2200 (1R) 2 5600/2200 (1R) 2 5600/2200 (1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (2R) 2 4400/2200 (2R) 2 4400/2200 (2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
UDIMM 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
SODIMM 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
RDIMM 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2 5600/2200 (1DPC 1R) 2   X 1 X X 3 X X 1 X X 3 X X 1 X X 3 X
4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2 4400/2200 (1DPC 2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
LPDDR5 Memory Format Component 5500/1600 (1R) 2 5500/1600 (1R) 2 5500/1600 (1R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
3200/1600 (2R) 2 3200/1600 (2R) 2 3200/1600 (2R) 2   X 1 X X 3   X 1 X X 3   X 1 X X 3  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS and QuestaSim.
  • 2 = Current performance in the Quartus® Prime software. Check the External Memory Interface Spec Estimator for production performance.
  • 3 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 5.   Intel Agilex® 7 M-Series HPS EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
Controller Hard controller X X X X X
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
AXI access mode Fabric sync mode          
Fabric async mode          
NoC X X X X X
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
DDR5 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
SODIMM, UDIMM X X X X X
RDIMM         X
Controller Hard controller X X X X X
3DS 3DS          
Design Example   X X X X  
DM DM pins X X X X X
AXI access mode Fabric sync mode          
Fabric async mode          
NoC X X X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
LPDDR5 Interface Width 32 X X X X  
16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
DM DM pins X X X X  
AXI access mode Fabric sync mode          
Fabric async mode          
NoC X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
  • Note: Address mirroring is handled by the controller when needed.

Known Issues in this Version

For a list of known issues affecting this release of the External Memory Interfaces Agilex™ 7 M-Series FPGA IP, follow this link to the: FPGA Knowledge Base.

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