External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

11.5.4. Using the EMIF Debug Toolkit

The main view of the EMIF Debug Toolkit contains the Memory Configuration, Calibration, Calibration Report, Driver Margining, VREF Margining, and Pin Delay Settings tabs.

Memory Configuration Tab

The Memory Configuration tab shows the IP settings, which you defined when you parameterized the EMIF IP.

Figure 77. Memory Configuration Tab

Calibration Tab

The Calibration tab allows you to rerun calibration and the test engine.

Figure 78. Calibration Tab