External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

Download PDF
ID 772538
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. s1_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s1_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s1_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. mem_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_ck_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_i3c for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. oct_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. PHY DFE Tap Bias Values for DDR5 7.4. MEM DFE Tap Bias Values for DDR5 7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.6. DDR5 Board Design Guidelines
7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.5.1.1. Estimating Pin Requirements 7.5.1.2. DIMM Options 7.5.1.3. Maximum Number of Interfaces
7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.5.2.1. OCT 7.5.2.2. PLL
7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.5.3.1. General Guidelines - DDR5 7.5.3.2. x4 DIMM Implementation 7.5.3.3. Specific Pin Connection Requirements 7.5.3.4. Command and Address Signals 7.5.3.5. Clock Signals 7.5.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.5.4.1. Address and Command Pin Placement for DDR5 7.5.4.2. DDR5 Data Width Mapping
7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.5.5.1. DDR5 Byte Lane Swapping 7.5.5.2. DDR5 Address and Command and CLK Lane 7.5.5.3. DDR5 Interface x8 Data Lane 7.5.5.4. DDR5 Interface x4 Data Lane 7.5.5.5. Pin Swizzling
7.6. DDR5 Board Design Guidelines x
7.6.1. PCB Stack-up and Design Considerations 7.6.2. General Design Considerations 7.6.3. DDR Differential Signals Routing 7.6.4. Ground Plane and Return Path 7.6.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.6.6. DRAM Break-in Layout Guidelines 7.6.7. General Notes for EMIF Routing Guidelines Tables 7.6.8. DDR5 PCB Layout Guidelines 7.6.9. DDR5 RDIMM Power Management IC 7.6.10. DDR5 Simulation Strategy
7.6.8. DDR5 PCB Layout Guidelines x
7.6.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.6.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.6.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.6.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 8.2. PHY DFE Tap Bias Values for LPDDR5 8.3. MEM DFE Tap Bias Values for LPDDR5 8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.5. LPDDR5 Board Design Guidelines
8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.4.1.1. Estimating Pin Requirements 8.4.1.2. LPDDR5 Component Options 8.4.1.3. Maximum Number of Interfaces
8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.4.2.1. OCT 8.4.2.2. PLL
8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.4.3.1. General Guidelines - LPDDR5 8.4.3.2. Specific Pin Connection Requirements 8.4.3.3. Command and Address Signals 8.4.3.4. Clock Signals
8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.4.4.1. Address and Command Pin Placement for LPDDR5 8.4.4.2. LPDDR5 Data Width Mapping 8.4.4.3. LPDDR5 Byte Lane Swapping
8.5. LPDDR5 Board Design Guidelines x
8.5.1. PCB Stack-up and Design Considerations 8.5.2. General Design Considerations 8.5.3. DDR Differential Signals Routing 8.5.4. Ground Plane and Return Path 8.5.5. DRAM Break-in Layout Guidelines 8.5.6. General Notes for EMIF Routing Guidelines Tables 8.5.7. LPDDR5 PCB Layout Guidelines 8.5.8. LPDDR5 Simulation Strategy
8.5.7. LPDDR5 PCB Layout Guidelines x
8.5.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.5.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.5.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes 10.4.3. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions 12.2. Sending a Mailbox Command
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes
12.2. Sending a Mailbox Command x
12.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox 12.2.2. Example 2: Reading the Memory Clock Frequency for an Interface 12.2.3. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP.
Table 178.  Group: High-level Configuration / Memory Device
Parameter Name Description
Number of Channels

Specifies the number of channels that the interface should implement. For multi-channel devices, this should always match the number of channels on the device.

Default value is 2

Legal values are: 1, 2, 4

(Identifier: MEM_NUM_CHANNELS)
Data DQ Width

Number of DQ pins per memory channel, used for data.

Default value is 16

Legal values are: 16, 32

(Identifier: MEM_CHANNEL_DATA_DQ_WIDTH)
Die Density

Capacity of each memory die (in Gbits), per channel per die. For dual-die packages, this is the density of each die, not the density of the full package.

Default value is 32

Legal values are: 2, 3, 4, 6, 8, 12, 16, 24, 32

(Identifier: MEM_DIE_DENSITY_GBITS)
CS Width

Specifies the total number of CS pins used by each channel.

Default value is 1

Legal values are: 1, 2

(Identifier: MEM_CHANNEL_CS_WIDTH)
Auto-set Memory Operating Frequency - FSP0

if true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_FSP0_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency - FSP0

Specifies the FSP0 operating frequency of the memory interface in MHz. This is not the same as boot-frequency (boot frequency is not a user parameter).

Legal values are: 800, 1066.667, 1375, 1600, 1866.667, 2133.333, 2400, 2750

(Identifier: MEM_FSP0_OPERATING_FREQ_MHZ)
Enable Frequency Set Point (FSP) 1

If true, users can enable and set values for a second frequency set point.

Default value is false

(Identifier: MEM_FSP1_EN)
Auto-set Memory Operating Frequency - FSP1

if true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_FSP1_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency - FSP1

Specifies the FSP1 operating frequency of the memory interface in MHz.

Legal values are: 800, 1066.667, 1375, 1600, 1866.667, 2133.333, 2400, 2750

(Identifier: MEM_FSP1_OPERATING_FREQ_MHZ)
Enable Frequency Set Point (FSP) 2

If true, users can enable and set values for a third frequency set point.

Default value is false

(Identifier: MEM_FSP2_EN)
Auto-set Memory Operating Frequency - FSP2

if true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_FSP2_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency - FSP2

Specifies the FSP2 operating frequency of the memory interface in MHz.

Legal values are: 800, 1066.667, 1375, 1600, 1866.667, 2133.333, 2400, 2750

(Identifier: MEM_FSP2_OPERATING_FREQ_MHZ)
Memory Operating Frequency

Specifies the frequency at which the memory interface will run.

(Identifier: MEM_OPERATING_FREQ_MHZ)
Table 179.  Group: High-level Configuration / PHY
Parameter Name Description
Auto-set PLL Reference Clock Frequency

if true, let IP select max PLL refclk frequency that this configuration can support. If false, user can set custom value for PLL refclk frequency.

Default value is true

(Identifier: PHY_REFCLK_FREQ_MHZ_AUTOSET_EN)
Enable Advanced List of PLL Reference Clock Frequencies

If true, provide extended list of possible refclk values. Otherwise, prune possible list of refclk values to a more reasonable length.

Default value is false

(Identifier: PHY_REFCLK_ADVANCED_SELECT_EN)
Reference Clock Frequency

Specifies the reference clock frequency for the EMIF IOPLL.

(Identifier: PHY_REFCLK_FREQ_MHZ)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms I/O BANK and TOP vs BOT part of the I/O BANK). Legal ranges are derived from device floorplan.

Default value is BOT

Legal values are: BOT, TOP, FULL

(Identifier: PHY_AC_PLACEMENT)
Auto-set Mainband Access Mode

if true, let IP select most likely usecase for the PHY_MAINBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN)
Mainband Access Mode

Specifies the path through which the EMIF QHIP mainband interface is exposed to the user. The mainband interface is the AXI4 interface to the memory controller.

Legal values are: NOC, ASYNC, SYNC

(Identifier: PHY_MAINBAND_ACCESS_MODE)
Auto-set Sideband Access Mode

if true, let IP select most likely usecase for the PHY_SIDEBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN)
Sideband Access Mode

Specifies the path through which the EMIF QHIP sideband interface is exposed to the user. The sideband interface is the AXI4-Lite interface to the IOSSM.

Legal values are: NOC, FABRIC

(Identifier: PHY_SIDEBAND_ACCESS_MODE)
Pin Swizzle Map

Specifies the swizzle map for the data lanes and pins.

(Identifier: PHY_SWIZZLE_MAP)
Use Debug Toolkit

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

Default value is false

(Identifier: DEBUG_TOOLS_EN)
Instance ID

Instance ID of the EMIF IP. This is useful when using a discovery mechanism over the side-band interface, to identify which EMIF instance's mailbox is at which offset. If expecting to use a discovery mechanism in hardware, this parameter must be set uniquely for all EMIFs that share a sideband. Otherwise, this parameter can be ignored / kept at the default value.

Default value is 0

Legal values are: from 0 to 6

(Identifier: INSTANCE_ID)
Table 180.  Group: High-level Configuration / Controller
Parameter Name Description
Use In-Line ECC

Specifies whether in-line ECC is enabled in the controller.

Default value is false

(Identifier: CTRL_ECC_INLINE_EN)
Use WR Link ECC

Specifies whether write link ECC is enabled in the controller.

Default value is false

(Identifier: CTRL_ECC_WR_LINK_EN)
Use RD Link ECC

Specifies whether read link ECC is enabled in the controller.

Default value is false

(Identifier: CTRL_ECC_RD_LINK_EN)
Use ECC Autocorrection

If ECC is enabled, specifies whether single-bit-errors (SBEs) should be corrected or just reported.

Default value is true

(Identifier: CTRL_ECC_AUTOCORRECT_EN)
Use Data Masking

Specifies whether Data Masking is enabled by the controller. When ECC is enabled, RMWs will occur (to recompute / write ECC), regardless of whether this is enabled.

Default value is false

(Identifier: CTRL_DM_EN)
Use WDBI

Specifies whether write Data-bus-inversion is enabled by the controller.

Default value is false

(Identifier: CTRL_WR_DBI_EN)
Use RDBI

Specifies whether read Data-bus-inversion is enabled by the controller.

Default value is false

(Identifier: CTRL_RD_DBI_EN)
Table 181.  Group: Advanced: Memory Timing / Overrides / JEDEC_TABLE
Parameter Name Description
JEDEC Parameter

Name of JEDEC Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: MEM_FSP0_CL_CYC, MEM_FSP1_CL_CYC, MEM_FSP2_CL_CYC, MEM_FSP0_CWL_CYC, MEM_FSP1_CWL_CYC, MEM_FSP2_CWL_CYC, MEM_RDQS_POSTAMBLE_MODE, MEM_RD_PREAMBLE_CYC, MEM_RD_POSTAMBLE_CYC, MEM_WR_POSTAMBLE_CYC, MEM_MINNUMREFSREQ, MEM_TRCD_NS, MEM_TRPAB_NS, MEM_TRPPB_NS, MEM_TRAS_NS, MEM_TRAS_MAX_NS, MEM_TWR_NS, MEM_FSP0_TRRD_L_NS, MEM_FSP1_TRRD_L_NS, MEM_FSP2_TRRD_L_NS, MEM_FSP0_TRRD_S_NS, MEM_FSP1_TRRD_S_NS, MEM_FSP2_TRRD_S_NS, MEM_TFAW_NS, MEM_FSP0_TRBTP_NS, MEM_FSP1_TRBTP_NS, MEM_FSP2_TRBTP_NS, MEM_FSP0_TWTR_S_NS, MEM_FSP1_TWTR_S_NS, MEM_FSP2_TWTR_S_NS, MEM_FSP0_TWTR_L_NS, MEM_FSP1_TWTR_L_NS, MEM_FSP2_TWTR_L_NS, MEM_FSP0_TPPD_NS, MEM_FSP1_TPPD_NS, MEM_FSP2_TPPD_NS, MEM_TRC_NS, MEM_TZQLAT_NS, MEM_TPW_RESET_NS, MEM_TERQE_NS, MEM_TERQX_NS, MEM_TRDQE_OD_NS, MEM_TRDQX_OD_NS, MEM_TRDQSTFE_NS, MEM_TRDQSTFX_NS, MEM_TCCDMW_NS, MEM_TREFW_NS, MEM_TREFI_NS, MEM_FSP0_TRFCAB_NS, MEM_FSP1_TRFCAB_NS, MEM_FSP2_TRFCAB_NS, MEM_FSP0_TRFCPB_NS, MEM_FSP1_TRFCPB_NS, MEM_FSP2_TRFCPB_NS, MEM_FSP0_TPBR2PBR_NS, MEM_FSP1_TPBR2PBR_NS, MEM_FSP2_TPBR2PBR_NS, MEM_TPBR2ACT_NS, MEM_FSP0_TCKCSH_NS, MEM_FSP1_TCKCSH_NS, MEM_FSP2_TCKCSH_NS, MEM_FSP0_TCMDPD_NS, MEM_FSP1_TCMDPD_NS, MEM_FSP2_TCMDPD_NS, MEM_FSP0_TXP_NS, MEM_FSP1_TXP_NS, MEM_FSP2_TXP_NS, MEM_TCSH_NS, MEM_FSP0_TCSLCK_NS, MEM_FSP1_TCSLCK_NS, MEM_FSP2_TCSLCK_NS, MEM_FSP0_TCSPD_NS, MEM_FSP1_TCSPD_NS, MEM_FSP2_TCSPD_NS, MEM_FSP0_TMRWPD_NS, MEM_FSP1_TMRWPD_NS, MEM_FSP2_TMRWPD_NS, MEM_FSP0_TZQPD_NS, MEM_FSP1_TZQPD_NS, MEM_FSP2_TZQPD_NS, MEM_FSP0_TESPD_NS, MEM_FSP1_TESPD_NS, MEM_FSP2_TESPD_NS, MEM_TSR_NS, MEM_TXSR_NS, MEM_FSP0_TMRR_NS, MEM_FSP1_TMRR_NS, MEM_FSP2_TMRR_NS, MEM_FSP0_TMRW_NS, MEM_FSP1_TMRW_NS, MEM_FSP2_TMRW_NS, MEM_FSP0_TMRD_NS, MEM_FSP1_TMRD_NS, MEM_FSP2_TMRD_NS, MEM_TOSCO_NS, MEM_TDQSCK_NS

(Identifier: JEDEC_OVERRIDE_TABLE_PARAM_NAME)
Table 182.  Group: Advanced: Memory Timing / Values
Parameter Name Description
[FSP0] Read Latency

[FSP0] Read Latency of the memory device in clock cycles.

(Identifier: MEM_FSP0_CL_CYC)
[FSP1] Read Latency

[FSP1] Read Latency of the memory device in clock cycles.

(Identifier: MEM_FSP1_CL_CYC)
[FSP2] Read Latency

[FSP2] Read Latency of the memory device in clock cycles.

(Identifier: MEM_FSP2_CL_CYC)
[FSP0] Write Latency

[FSP0] Write Latency in clock cycles.

(Identifier: MEM_FSP0_CWL_CYC)
[FSP1] Write Latency

[FSP1] Write Latency in clock cycles.

(Identifier: MEM_FSP1_CWL_CYC)
[FSP2] Write Latency

[FSP2] Write Latency in clock cycles.

(Identifier: MEM_FSP2_CWL_CYC)
Read Postamble Mode

RDQS Postamble Mode.

(Identifier: MEM_RDQS_POSTAMBLE_MODE)
Read Preamble Cycles

RDQS Preamble length (in cycles).

(Identifier: MEM_RD_PREAMBLE_CYC)
Read Postamble Cycles

RDQS Postamble length (in cycles).

(Identifier: MEM_RD_POSTAMBLE_CYC)
Write Postamble Cycles

WCK Postamble length (in cycles).

(Identifier: MEM_WR_POSTAMBLE_CYC)
Min Number of Refs Reqd

Minimum Number of Refreshes Required.

(Identifier: MEM_MINNUMREFSREQ)
tRCD

RAS-to-CAS Delay in nanoseconds.

(Identifier: MEM_TRCD_NS)
tRPab

All-Bank Precharge Time in nanoseconds.

(Identifier: MEM_TRPAB_NS)
tRPpb

Per-Bank Precharge Time in nanoseconds.

(Identifier: MEM_TRPPB_NS)
tRAS

Row Active Time in nanoseconds.

(Identifier: MEM_TRAS_NS)
tRAS_MAX

Specifies the maximum Activate-to-Precharge command period in nanoseconds.

(Identifier: MEM_TRAS_MAX_NS)
tWR

Write Recovery Time in nanoseconds.

(Identifier: MEM_TWR_NS)
[FSP0] tRRD_L

[FSP0] RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in nanoseconds.

(Identifier: MEM_FSP0_TRRD_L_NS)
[FSP1] tRRD_L

[FSP1] RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in nanoseconds.

(Identifier: MEM_FSP1_TRRD_L_NS)
[FSP2] tRRD_L

[FSP2] RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in nanoseconds.

(Identifier: MEM_FSP2_TRRD_L_NS)
[FSP0] tRRD_S

[FSP0] RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in nanoseconds.

(Identifier: MEM_FSP0_TRRD_S_NS)
[FSP1] tRRD_S

[FSP1] RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in nanoseconds.

(Identifier: MEM_FSP1_TRRD_S_NS)
[FSP2] tRRD_S

[FSP2] RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in nanoseconds.

(Identifier: MEM_FSP2_TRRD_S_NS)
tFAW

Four-bank ACTIVE window time in nanoseconds.

(Identifier: MEM_TFAW_NS)
[FSP0] tRBTP

[FSP0] Read Burst End to Precharge Command Delay in nanoseconds.

(Identifier: MEM_FSP0_TRBTP_NS)
[FSP1] tRBTP

[FSP1] Read Burst End to Precharge Command Delay in nanoseconds.

(Identifier: MEM_FSP1_TRBTP_NS)
[FSP2] tRBTP

[FSP2] Read Burst End to Precharge Command Delay in nanoseconds.

(Identifier: MEM_FSP2_TRBTP_NS)
[FSP0] tWTR_S

[FSP0] Write-to-Read Delay (Short) in nanoseconds.

(Identifier: MEM_FSP0_TWTR_S_NS)
[FSP1] tWTR_S

[FSP1] Write-to-Read Delay (Short) in nanoseconds.

(Identifier: MEM_FSP1_TWTR_S_NS)
[FSP2] tWTR_S

[FSP2] Write-to-Read Delay (Short) in nanoseconds.

(Identifier: MEM_FSP2_TWTR_S_NS)
[FSP0] tWTR_L

[FSP0] Write-to-Read Delay (Long) in nanoseconds.

(Identifier: MEM_FSP0_TWTR_L_NS)
[FSP1] tWTR_L

[FSP1] Write-to-Read Delay (Long) in nanoseconds.

(Identifier: MEM_FSP1_TWTR_L_NS)
[FSP2] tWTR_L

[FSP2] Write-to-Read Delay (Long) in nanoseconds.

(Identifier: MEM_FSP2_TWTR_L_NS)
[FSP0] tPPD

[FSP0] Precharge-to-precharge delay in nanoseconds.

(Identifier: MEM_FSP0_TPPD_NS)
[FSP1] tPPD

[FSP1] Precharge-to-precharge delay in nanoseconds.

(Identifier: MEM_FSP1_TPPD_NS)
[FSP2] tPPD

[FSP2] Precharge-to-precharge delay in nanoseconds.

(Identifier: MEM_FSP2_TPPD_NS)
tRC

Activate-to-Activate command period (same bank) in nanoseconds.

(Identifier: MEM_TRC_NS)
tZQLAT

ZQCAL Latch Quiet Time in nanoseconds.

(Identifier: MEM_TZQLAT_NS)
tPW_RESET

Min RESET_n low time for Reset Initialization with Stable Power Time in nanoseconds.

(Identifier: MEM_TPW_RESET_NS)
tERQE

Enhanced RDQS Toggle Mode Entry Time in nanoseconds.

(Identifier: MEM_TERQE_NS)
tERQX

Enhanced RDQS Toggle Mode Exit Time in nanoseconds.

(Identifier: MEM_TERQX_NS)
tRDQE_OD

ODT-disable from Enhanced RDQS Toggle Mode Entry Time in nanoseconds.

(Identifier: MEM_TRDQE_OD_NS)
tRDQX_OD

ODT-enable from Enhanced RDQS Toggle Mode Exit Time in nanoseconds.

(Identifier: MEM_TRDQX_OD_NS)
tRDQSTFE

Read/Write-based RDQS_t Training Mode Entry Time in nanoseconds.

(Identifier: MEM_TRDQSTFE_NS)
tRDQSTFX

Read/Write-based RDQS_t Training Mode Exit Time in nanoseconds.

(Identifier: MEM_TRDQSTFX_NS)
tCCDMW

CAS-to-CAS Delay for Masked Write in nanoseconds.

(Identifier: MEM_TCCDMW_NS)
tREFW

Refresh Window in nanoseconds.

(Identifier: MEM_TREFW_NS)
tREFI

Refresh Interval Time in nanoseconds.

(Identifier: MEM_TREFI_NS)
[FSP0] tRFCab

[FSP0] All-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_FSP0_TRFCAB_NS)
[FSP1] tRFCab

[FSP1] All-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_FSP1_TRFCAB_NS)
[FSP2] tRFCab

[FSP2] All-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_FSP2_TRFCAB_NS)
[FSP0] tRFCpb

[FSP0] Per-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_FSP0_TRFCPB_NS)
[FSP1] tRFCpb

[FSP1] Per-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_FSP1_TRFCPB_NS)
[FSP2] tRFCpb

[FSP2] Per-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_FSP2_TRFCPB_NS)
[FSP0] tpbR2pbR

[FSP0] Per-Bank Refresh to Per-Bank Refresh minimum interval time in nanoseconds.

(Identifier: MEM_FSP0_TPBR2PBR_NS)
[FSP1] tpbR2pbR

[FSP1] Per-Bank Refresh to Per-Bank Refresh minimum interval time in nanoseconds.

(Identifier: MEM_FSP1_TPBR2PBR_NS)
[FSP2] tpbR2pbR

[FSP2] Per-Bank Refresh to Per-Bank Refresh minimum interval time in nanoseconds.

(Identifier: MEM_FSP2_TPBR2PBR_NS)
tpbR2ACT

Per-Bank Refresh to Activate minimum interval time in nanoseconds.

(Identifier: MEM_TPBR2ACT_NS)
[FSP0] tCKCSH

[FSP0] Valid Clock Requirement before CS goes High (Power-Down AC Timings) in nanoseconds.

(Identifier: MEM_FSP0_TCKCSH_NS)
[FSP1] tCKCSH

[FSP1] Valid Clock Requirement before CS goes High (Power-Down AC Timings) in nanoseconds.

(Identifier: MEM_FSP1_TCKCSH_NS)
[FSP2] tCKCSH

[FSP2] Valid Clock Requirement before CS goes High (Power-Down AC Timings) in nanoseconds.

(Identifier: MEM_FSP2_TCKCSH_NS)
[FSP0] tCMDPD

[FSP0] Delay from valid command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP0_TCMDPD_NS)
[FSP1] tCMDPD

[FSP1] Delay from valid command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP1_TCMDPD_NS)
[FSP2] tCMDPD

[FSP2] Delay from valid command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP2_TCMDPD_NS)
[FSP0] tXP

[FSP0] Exit Power-Down to Next Valid Command Delay Time in nanoseconds.

(Identifier: MEM_FSP0_TXP_NS)
[FSP1] tXP

[FSP1] Exit Power-Down to Next Valid Command Delay Time in nanoseconds.

(Identifier: MEM_FSP1_TXP_NS)
[FSP2] tXP

[FSP2] Exit Power-Down to Next Valid Command Delay Time in nanoseconds.

(Identifier: MEM_FSP2_TXP_NS)
tCSH

Minimum CS High Pulse Width at Power Down Exit in nanoseconds.

(Identifier: MEM_TCSH_NS)
[FSP0] tCSLCK

[FSP0] Valid Clock Requirement after Power Down Entry in nanoseconds.

(Identifier: MEM_FSP0_TCSLCK_NS)
[FSP1] tCSLCK

[FSP1] Valid Clock Requirement after Power Down Entry in nanoseconds.

(Identifier: MEM_FSP1_TCSLCK_NS)
[FSP2] tCSLCK

[FSP2] Valid Clock Requirement after Power Down Entry in nanoseconds.

(Identifier: MEM_FSP2_TCSLCK_NS)
[FSP0] tCSPD

[FSP0] Delay time from Power Down Entry to CS going High in nanoseconds.

(Identifier: MEM_FSP0_TCSPD_NS)
[FSP1] tCSPD

[FSP1] Delay time from Power Down Entry to CS going High in nanoseconds.

(Identifier: MEM_FSP1_TCSPD_NS)
[FSP2] tCSPD

[FSP2] Delay time from Power Down Entry to CS going High in nanoseconds.

(Identifier: MEM_FSP2_TCSPD_NS)
[FSP0] tMRWPD

[FSP0] Delay from MRW Command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP0_TMRWPD_NS)
[FSP1] tMRWPD

[FSP1] Delay from MRW Command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP1_TMRWPD_NS)
[FSP2] tMRWPD

[FSP2] Delay from MRW Command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP2_TMRWPD_NS)
[FSP0] tZQPD

[FSP0] Delay from ZQ Calibration Start/Latch Command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP0_TZQPD_NS)
[FSP1] tZQPD

[FSP1] Delay from ZQ Calibration Start/Latch Command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP1_TZQPD_NS)
[FSP2] tZQPD

[FSP2] Delay from ZQ Calibration Start/Latch Command to Power Down Entry in nanoseconds.

(Identifier: MEM_FSP2_TZQPD_NS)
[FSP0] tESPD

[FSP0] Delay time from Self-Refresh Entry command to Power Down Entry command in nanoseconds.

(Identifier: MEM_FSP0_TESPD_NS)
[FSP1] tESPD

[FSP1] Delay time from Self-Refresh Entry command to Power Down Entry command in nanoseconds.

(Identifier: MEM_FSP1_TESPD_NS)
[FSP2] tESPD

[FSP2] Delay time from Self-Refresh Entry command to Power Down Entry command in nanoseconds.

(Identifier: MEM_FSP2_TESPD_NS)
tSR

Minimum Self-Refresh Time (Entry to Exit) in nanoseconds.

(Identifier: MEM_TSR_NS)
tXSR

Exit Self-Refresh time in nanoseconds.

(Identifier: MEM_TXSR_NS)
[FSP0] tMRR

[FSP0] Mode Register Read Command Period Time in nanoseconds.

(Identifier: MEM_FSP0_TMRR_NS)
[FSP1] tMRR

[FSP1] Mode Register Read Command Period Time in nanoseconds.

(Identifier: MEM_FSP1_TMRR_NS)
[FSP2] tMRR

[FSP2] Mode Register Read Command Period Time in nanoseconds.

(Identifier: MEM_FSP2_TMRR_NS)
[FSP0] tMRW

[FSP0] Mode Register Write Command Period Time in nanoseconds.

(Identifier: MEM_FSP0_TMRW_NS)
[FSP1] tMRW

[FSP1] Mode Register Write Command Period Time in nanoseconds.

(Identifier: MEM_FSP1_TMRW_NS)
[FSP2] tMRW

[FSP2] Mode Register Write Command Period Time in nanoseconds.

(Identifier: MEM_FSP2_TMRW_NS)
[FSP0] tMRD

[FSP0] Mode Register Set Command Period Time in nanoseconds.

(Identifier: MEM_FSP0_TMRD_NS)
[FSP1] tMRD

[FSP1] Mode Register Set Command Period Time in nanoseconds.

(Identifier: MEM_FSP1_TMRD_NS)
[FSP2] tMRD

[FSP2] Mode Register Set Command Period Time in nanoseconds.

(Identifier: MEM_FSP2_TMRD_NS)
tOSCO

Delay time from Stop WCK2DQI/WCK2DQO Interval Oscillator Command to Mode Register Readout time in nanoseconds.

(Identifier: MEM_TOSCO_NS)
tDQSCK

DQS output access time from CK in nanoseconds.

(Identifier: MEM_TDQSCK_NS)
Table 183.  Group: Advanced: Analog Overrides / Overrides / ANALOG_TABLE
Parameter Name Description
Analog Parameter

Name of Analog Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: PHY_TERM_X_R_S_AC_OUTPUT_OHM, PHY_TERM_X_R_S_CK_OUTPUT_OHM, PHY_TERM_X_R_S_DQ_OUTPUT_OHM, PHY_TERM_X_DQ_SLEW_RATE, PHY_TERM_X_R_T_DQ_INPUT_OHM, PHY_TERM_X_DQ_VREF, PHY_TERM_X_R_T_REFCLK_INPUT_OHM, PHY_DFE_X_TAP_1, PHY_DFE_X_TAP_2, PHY_DFE_X_TAP_3, PHY_DFE_X_TAP_4, MEM_ODT_DQ_X_TGT_WR, MEM_ODT_DQ_X_NON_TGT, MEM_ODT_DQ_X_RON, MEM_ODT_DQ_X_WCK, MEM_VREF_DQ_X_VALUE, MEM_ODT_CA_X_CA_COMM, MEM_ODT_CA_X_CA_ENABLE, MEM_ODT_CA_X_CS_ENABLE, MEM_ODT_CA_X_CK_ENABLE, MEM_VREF_CA_X_CA_VALUE, MEM_DFE_X_TAP_1

(Identifier: ANALOG_PARAM_DERIVATION_PARAM_NAME)
Table 184.  Group: Advanced: Analog Overrides / Values
Parameter Name Description
AC Drive Strength

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_AC_OUTPUT_OHM)
CK Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_CK_OUTPUT_OHM)
DQ I/O Standard

Specifies the I/O electrical standard for the data bus pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard.

(Identifier: PHY_TERM_X_DQ_IO_STD_TYPE)
FPGA DQ Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_DQ_OUTPUT_OHM)
DQ Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

Legal values are: SLOW, MEDIUM, FAST, FASTEST

(Identifier: PHY_TERM_X_DQ_SLEW_RATE)
DQ Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: RT_40_OHM_CAL, RT_50_OHM_CAL, RT_60_OHM_CAL

(Identifier: PHY_TERM_X_R_T_DQ_INPUT_OHM)
DQ Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

Legal values are: from 0.0 to 100.0

(Identifier: PHY_TERM_X_DQ_VREF)
PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: RT_OFF, RT_DIFF

(Identifier: PHY_TERM_X_R_T_REFCLK_INPUT_OHM)
PHY DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the FPGA DFE.

Legal values are: 0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31.

Note: Refer to Table 189 in the PHY DFE Tap Bias Values for LPDDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_1)
PHY DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the FPGA DFE.

Legal values are: p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8.

Note: Refer to Table 189 in the PHY DFE Tap Bias Values for LPDDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_2)
PHY DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the FPGA DFE.

Legal values are: p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8.

Note: Refer to Table 189 in the PHY DFE Tap Bias Values for LPDDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_3)
PHY DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the FPGA DFE.

Legal values are: p3, p2, p1, 0, n1, n2, n3, n4.

Note: Refer to Table 189 in the PHY DFE Tap Bias Values for LPDDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_4)
Target Write Termination

Specifies the target termination to be used during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6

(Identifier: MEM_ODT_DQ_X_TGT_WR)
DQ Non-Target Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6

(Identifier: MEM_ODT_DQ_X_NON_TGT)
Memory DQ Drive Strength

Specifies the termination to be used when driving read data from memory. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: 6, 5, 4, 3, 2, 1

(Identifier: MEM_ODT_DQ_X_RON)
Data Clock Termination

Specifies the termination to be used for the data clock (WCK). The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6

(Identifier: MEM_ODT_DQ_X_WCK)
VrefDQ Value

Specifies the initial VrefDQ value to be used.

Legal values are: from 10.0 to 73.5

(Identifier: MEM_VREF_DQ_X_VALUE)
CA Common Termination

Common termination value that can be applied to CA/CK. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: off, 1, 2, 3, 4, 5, 6

(Identifier: MEM_ODT_CA_X_CA_COMM)
CA Termination Enable

Enable the common termination value on the CA bus. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: false, true

(Identifier: MEM_ODT_CA_X_CA_ENABLE)
CS Termination Enable

For LPDDR5, this enables the fixed-value 80 Ohm (RZQ/3) CS termination if it is supported by the memory. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: false, true

(Identifier: MEM_ODT_CA_X_CS_ENABLE)
CK Termination Enable

Enable the common termination value on the CK bus. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: false, true

(Identifier: MEM_ODT_CA_X_CK_ENABLE)
VrefCA Value

Specifies the initial VrefCA value to be used.

Legal values are: from 10.0 to 73.5

(Identifier: MEM_VREF_CA_X_CA_VALUE)
MEM DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the memory DFE.

Legal values are: 0, n1, n2, n3.

Note: Refer to Table 190 in the MEM DFE Tap Bias Values for LPDDR5 topic for actual bias values.

(Identifier: MEM_DFE_X_TAP_1)
Table 185.  Group: Example Design / Fileset Types
Parameter Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

Default value is VERILOG

Legal values are: VERILOG, VHDL

(Identifier: EX_DESIGN_HDL_FORMAT)
Generate Synthesis Fileset

Generate Synthesis Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SYNTH)
Generate Simulation Fileset

Generate Simulation Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SIM)
Table 186.  Group: Example Design / User PLL
Parameter Name Description
Auto-set User PLL Output Clock Frequency

if true, let IP select a reference clock frequency for the user PLL in the example design; if false, let user set a custom value for this parameter.

Default value is true

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN)
User PLL Output Clock Frequency

Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode).

Default value is 570

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ)
User PLL Reference Clock Frequency

PLL reference clock frequency in MHz for PLL supplying the core clock.

Default value is 100

(Identifier: EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ)
NOC Reference Clock Frequency

Reference Clock Frequency for the NOC control IP.

Default value is 100

Legal values are: 25, 100, 125

(Identifier: EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ)
Table 187.  Group: Example Design / Traffic Generator
Parameter Name Description
Traffic Generator Remote Access

Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled.

Default value is JTAG

Legal values are: EXPORT, JTAG

(Identifier: EX_DESIGN_TG_CSR_ACCESS_MODE)
Traffic Generator Program

Specifies the traffic pattern to be run.

Default value is MEDIUM

Legal values are: SHORT, MEDIUM, LONG, INFINITE

(Identifier: EX_DESIGN_TG_PROGRAM)
Table 188.  Group: Example Design / Performance Monitor
Parameter Name Description
Enable Performance Monitor for Channel 0

If true, example design will include a Performance Monitor instance connected to Channel 0.

Default value is false

(Identifier: EX_DESIGN_PMON_CH0_EN)
Enable Performance Monitor for Channel 1

If true, example design will include a Performance Monitor instance connected to Channel 1.

Default value is false

(Identifier: EX_DESIGN_PMON_CH1_EN)
Enable Performance Monitor for Channel 2

If true, example design will include a Performance Monitor instance connected to Channel 2.

Default value is false

(Identifier: EX_DESIGN_PMON_CH2_EN)
Enable Performance Monitor for Channel 3

If true, example design will include a Performance Monitor instance connected to Channel 3.

Default value is false

(Identifier: EX_DESIGN_PMON_CH3_EN)
Level Two Title