FPGA AI Suite Version 2024.3 adds the following new features and enhancements:

• The FPGA AI Suite now supports Upsampling and Downsampling (nearest neighbor) with factors of 2 and 4.
• Running the dla_compiler command with the --fanalyze-area option now produces a .ptc file that you can open in the Quartus Power and Thermal Calculator (PTC), for estimating the power consumption of a particular architecture. (The PTC supports power estimation on Agilex™ 5, Agilex™ 7, and Stratix® 10 devices only.)
• The Model Analyzer now reports which aux modules can be safely disabled in an architecture when a graph does not require them. Improvements have also been made to the Model Analyzer .dot graphs to include more information from the text report files.
• The hardware input layout transform, which was previously released as an early access feature, is now available as a production feature. More information about this feature is provided in the FPGA AI Suite IP Reference Manual .

Multilane

• The new num_lanes architecture parameter provides parallelism across height for compatible layers.
  Using the num_lanes architecture parameter has the following effects:

  • Setting the num_lanes parameter scales the PE array in the FPGA AI Suite IP by the given number and provides additional parallelism at the cost of more DSPs and area.
  • The total stream buffer size scales with the num_lanes parameter. Because the feature surface of a graph is divided across multiple lanes, Altera recommends adjusting the stream_buffer_depth parameter listed in the .arch file by the inverse of the num_lanes parameter value. For example, a 4-lane architecture with 10k stream buffer depth indicates a 40k total stream buffer size.
• For FPGA AI Suite Version 2024.3, Altera recommends using multilane with the DDR-free inference option.

Design Examples

• The amount of RAM for the Agilex™ 7 SoC design example has been increased from 1GB to 8GB.
• The root file system size has increased for the SoC design examples as follows:
  • The Agilex™ 7 SoC design example root file system is now 4 GB.
  • The Arria® 10 SoC design example root file system is now 2 GB.
• The following example designs are added in FPGA AI Suite Version 2024.3:
  • Hostless design example on Agilex™ 5 E-Series 065B Premium Development Kit. This example design relies on JTAG for host-FPGA communication.
  • PCIe-attach design example on Intel® FPGA SmartNIC N6001-PL Platform (without an Ethernet controller).
  • PCIe-attach design example on Agilex™ 7 FPGA I-Series Development Kit (DK-DEV-AGI027RBES).