4. Known Issues and Workarounds
FPGA AI Suite Version 2024.3 has the following known issues:
- When the input layout transform is enabled, the area estimates for some IP architectures can be too low.
- Building the Arria® 10 SoC design example on a Red Hat Enterprise Linux system requires Red Hat Enterprise Linux 8.10.
- The area model reports the wrong DSP configuration with Agilex™ 5 architectures.
The area model reports the DSP configuration being "Sum of 4 9x9" when it is a DSP tensor mode. This reporting results in a "PTC Import Warning" when you use a .ptc file generated from an Agilex 5 architecture.
- The AGX7_Streaming_Ddrfree_Multilane architecture file does not have a pool aux module. This lack of the pool aux module can produce dla_compiler errors on graphs that require pooling, for example, ResNet18 and ResNet50.
- If you use the hardware layout transform, then the max_feature_height parameter must be greater than or equal to the channel dimension of your graph. This limitation is due to a known issue with the parameter checks that causes the the input graph channel dimension to be compared against the max_feature_height instead of the max_channels value.
Streaming Flow Known Issues and Workarounds
- Only single-output graphs are supported.
- MobileNet-v2 is known to fail in the streaming flow when no external memory is used.
Multilane
- The num_lanes parameter takes only the values 1, 2, or 4.
- When an architecture has a num_lanes parameter value greater than 1, the architecture has the following restrictions:
- All k_vector and c_vector parameter values in the architecture must be the same.
- The softmax auxiliary module is not supported.
- Multilane exhibits low performance when used with DDR when a graph has residual connections.