Parameterizable Macros for Intel® FPGAs User Guide

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ID 772350
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Parameterizable Macros for Intel FPGAs Overview 2. Dual-Port Random Access Memory (RAM) Parameterizable Macros 3. FIFO Parameterizable Macros 4. I/O PLL Parameterizable Macro (ipm_iopll) 5. CDC Parameterizable Macros 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 7. Parameterizable Macros for Intel FPGAs User Guide Archives
1. Parameterizable Macros for Intel FPGAs Overview x
1.1. Available Parameterizable Macros for Intel FPGAs 1.2. Inserting HDL Code from Parameterizable Macro Templates
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
2.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) 2.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram)
2.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) x
2.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions 2.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters 2.1.3. Simple Dual-Port RAM VHDL Instantiation Template 2.1.4. Simple Dual-Port RAM Verilog Instantiation Template 2.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
2.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram) x
2.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions 2.2.2. True Dual-Port RAM Parameterizable Macro Parameters 2.2.3. True Dual-Port RAM VHDL Instantiation Template 2.2.4. True Dual-Port RAM Verilog Instantiation Template 2.2.5. True Dual-Port RAM SystemVerilog Instantiation Template
3. FIFO Parameterizable Macros x
3.1. Synchronous FIFO Parameterizable Macro (sync_fifo) 3.2. Asynchronous FIFO Parameterizable Macro (async_fifo)
3.1. Synchronous FIFO Parameterizable Macro (sync_fifo) x
3.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions 3.1.2. Synchronous FIFO Parameterizable Macro Parameters 3.1.3. Synchronous FIFO VHDL Instantiation Template 3.1.4. Synchronous FIFO Verilog Instantiation Template 3.1.5. Synchronous FIFO SystemVerilog Instantiation Template
3.2. Asynchronous FIFO Parameterizable Macro (async_fifo) x
3.2.1. Asynchronous FIFO Parameterizable Macro Port Descriptions 3.2.2. Asynchronous FIFO Parameterizable Macro Parameters 3.2.3. Asynchronous FIFO VHDL Instantiation Template 3.2.4. Asynchronous FIFO Verilog Instantiation Template 3.2.5. Asynchronous FIFO SystemVerilog Instantiation Template
4. I/O PLL Parameterizable Macro (ipm_iopll) x
4.1. I/O PLL Parameterizable Macro Operating Modes 4.2. I/O PLL Parameterizable Macro Port Descriptions 4.3. I/O PLL Parameterizable Macro Parameters 4.4. I/O PLL VHDL Instantiation Template 4.5. I/O PLL Verilog Instantiation Template 4.6. I/O PLL SystemVerilog Instantiation Template
5. CDC Parameterizable Macros x
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) 5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) 5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) 5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) 5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) 5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) 5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync)
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) x
5.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions 5.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters 5.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template 5.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template 5.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) x
5.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions 5.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters 5.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template 5.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template 5.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) x
5.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions 5.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters 5.3.3. Synchronizer Using Single Clock VHDL Instantiation Template 5.3.4. Synchronizer Using Single Clock Verilog Instantiation Template 5.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) x
5.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions 5.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters 5.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template 5.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template 5.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) x
5.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions 5.5.2. Glitchless Clock MUX Parameterizable Macro Parameters 5.5.3. Glitchless Clock MUX VHDL Instantiation Template 5.5.4. Glitchless Clock MUX Verilog Instantiation Template 5.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) x
5.6.1. Bus Synchronizer Parameterizable Macro Port Descriptions 5.6.2. Bus Synchronizer Parameterizable Macro Parameters 5.6.3. Bus Synchronizer VHDL Instantiation Template 5.6.4. Bus Synchronizer Verilog Instantiation Template 5.6.5. Bus Synchronizer SystemVerilog Instantiation Template
5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync) x
5.7.1. Pulse Synchronizer Parameterizable Macro Ports 5.7.2. Pulse Synchronizer Parameterizable Macro Parameters 5.7.3. Pulse Synchronizer VHDL Instantiation Template 5.7.4. Pulse Synchronizer Verilog Instantiation Template 5.7.5. Pulse Synchronizer SystemVerilog Instantiation Template
Answers to Top FAQs
1. Parameterizable Macros for Intel FPGAs Overview
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros
3. FIFO Parameterizable Macros
4. I/O PLL Parameterizable Macro (ipm_iopll)
5. CDC Parameterizable Macros
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
7. Parameterizable Macros for Intel FPGAs User Guide Archives

4. I/O PLL Parameterizable Macro (ipm_iopll)

I/O PLL parameterizable macro allows you to readily configure the settings of the I/O PLL. An I/O PLL is a frequency-control system that generates an output clock by synchronizing itself to an input clock. The PLL compares the phase difference between the input signal and the output signal of a voltage-controlled oscillator (VCO) and then performs phase synchronization to maintain a constant phase angle (lock) on the frequency of the input or reference signal. The synchronization or negative feedback loop of the system forces the PLL to be phase locked.

You can configure PLLs as frequency multipliers, dividers, demodulators, tracking generators, or clock recovery circuits. You can use PLLs to generate stable frequencies, recover signals from a noisy communication channel, or distribute clock signals throughout your design.

Figure 6. I/O PLL Parameterizable Macro Block Diagram


The I/O PLL macro (ipm_iopll) generates up to seven output clock frequencies with respect to the input reference clock, and can generate up to nine clock output signals. The generated clock output signals clock the core or the external blocks outside the core. Computation codes are used to calculate the expected clock frequencies and to compute the physical parameter values (divide N counter, divide M counter and divide C counters) of the I/O PLL for functional correctness.

The PLL lock is dependent on the two input signals in the phase frequency detector. The lock signal is an asynchronous output of the PLLs. The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal

The ipm_iopll macro supports the following:

  • Supports removal of added delays in the feedback clock network by selecting the suitable compensation or operation modes.
  • Supports various clock feedback operating modes to compensate for clock network delays to align the rising edge of the output clock with the rising edge of the PLL’s reference clock, as I/O PLL Parameterizable Macro Operating Modes describes
  • Supports variable phase shifts of outclks. Currently supported phase shifts in the macro are 0, 90, 180 and 270 degrees.

This section provides the port descriptions, parameter tables, and instantiation templates for this parameterizable macro.


Section Content
I/O PLL Parameterizable Macro Operating Modes
I/O PLL Parameterizable Macro Port Descriptions
I/O PLL Parameterizable Macro Parameters
I/O PLL VHDL Instantiation Template
I/O PLL Verilog Instantiation Template
I/O PLL SystemVerilog Instantiation Template

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