Parameterizable Macros for Intel® FPGAs User Guide

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Date 4/10/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Parameterizable Macros for Intel FPGAs Overview 2. Dual-Port Random Access Memory (RAM) Parameterizable Macros 3. FIFO Parameterizable Macros 4. I/O PLL Parameterizable Macro (ipm_iopll) 5. CDC Parameterizable Macros 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 7. Parameterizable Macros for Intel FPGAs User Guide Archives
1. Parameterizable Macros for Intel FPGAs Overview x
1.1. Available Parameterizable Macros for Intel FPGAs 1.2. Inserting HDL Code from Parameterizable Macro Templates
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
2.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) 2.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram)
2.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) x
2.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions 2.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters 2.1.3. Simple Dual-Port RAM VHDL Instantiation Template 2.1.4. Simple Dual-Port RAM Verilog Instantiation Template 2.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
2.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram) x
2.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions 2.2.2. True Dual-Port RAM Parameterizable Macro Parameters 2.2.3. True Dual-Port RAM VHDL Instantiation Template 2.2.4. True Dual-Port RAM Verilog Instantiation Template 2.2.5. True Dual-Port RAM SystemVerilog Instantiation Template
3. FIFO Parameterizable Macros x
3.1. Synchronous FIFO Parameterizable Macro (sync_fifo) 3.2. Asynchronous FIFO Parameterizable Macro (async_fifo)
3.1. Synchronous FIFO Parameterizable Macro (sync_fifo) x
3.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions 3.1.2. Synchronous FIFO Parameterizable Macro Parameters 3.1.3. Synchronous FIFO VHDL Instantiation Template 3.1.4. Synchronous FIFO Verilog Instantiation Template 3.1.5. Synchronous FIFO SystemVerilog Instantiation Template
3.2. Asynchronous FIFO Parameterizable Macro (async_fifo) x
3.2.1. Asynchronous FIFO Parameterizable Macro Port Descriptions 3.2.2. Asynchronous FIFO Parameterizable Macro Parameters 3.2.3. Asynchronous FIFO VHDL Instantiation Template 3.2.4. Asynchronous FIFO Verilog Instantiation Template 3.2.5. Asynchronous FIFO SystemVerilog Instantiation Template
4. I/O PLL Parameterizable Macro (ipm_iopll) x
4.1. I/O PLL Parameterizable Macro Operating Modes 4.2. I/O PLL Parameterizable Macro Port Descriptions 4.3. I/O PLL Parameterizable Macro Parameters 4.4. I/O PLL VHDL Instantiation Template 4.5. I/O PLL Verilog Instantiation Template 4.6. I/O PLL SystemVerilog Instantiation Template
5. CDC Parameterizable Macros x
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) 5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) 5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) 5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) 5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) 5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) 5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync)
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) x
5.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions 5.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters 5.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template 5.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template 5.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) x
5.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions 5.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters 5.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template 5.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template 5.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) x
5.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions 5.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters 5.3.3. Synchronizer Using Single Clock VHDL Instantiation Template 5.3.4. Synchronizer Using Single Clock Verilog Instantiation Template 5.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) x
5.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions 5.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters 5.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template 5.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template 5.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) x
5.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions 5.5.2. Glitchless Clock MUX Parameterizable Macro Parameters 5.5.3. Glitchless Clock MUX VHDL Instantiation Template 5.5.4. Glitchless Clock MUX Verilog Instantiation Template 5.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) x
5.6.1. Bus Synchronizer Parameterizable Macro Port Descriptions 5.6.2. Bus Synchronizer Parameterizable Macro Parameters 5.6.3. Bus Synchronizer VHDL Instantiation Template 5.6.4. Bus Synchronizer Verilog Instantiation Template 5.6.5. Bus Synchronizer SystemVerilog Instantiation Template
5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync) x
5.7.1. Pulse Synchronizer Parameterizable Macro Ports 5.7.2. Pulse Synchronizer Parameterizable Macro Parameters 5.7.3. Pulse Synchronizer VHDL Instantiation Template 5.7.4. Pulse Synchronizer Verilog Instantiation Template 5.7.5. Pulse Synchronizer SystemVerilog Instantiation Template
Answers to Top FAQs
1. Parameterizable Macros for Intel FPGAs Overview
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros
3. FIFO Parameterizable Macros
4. I/O PLL Parameterizable Macro (ipm_iopll)
5. CDC Parameterizable Macros
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
7. Parameterizable Macros for Intel FPGAs User Guide Archives

3.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions

Table 5.  Synchronous FIFO Parameterizable Macro Port Descriptions
Port Type Required Description
clock Input Yes Positive-edge-triggered clock.
data Input Yes Holds the data to be written in the FIFO when the wrreq signal is asserted. The port width is equal to the DATA_WIDTH parameter.
wrreq Input Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

  • Do not assert the wrreq signal when the full port is high. Enable the overflow protection circuitry or set the OVERFLOW_CHECKING parameter to ON so that the FIFO can automatically disable the wrreq signal when it is full.
  • The wrreq signal must meet the functional timing requirement based on the full signal.
  • Do not assert the wrreq signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr signal and the rising edge of the write clock if the wrreq port is set to high.
rdreq Input Yes Assert this signal to request for a read operation. The rdreq signal acts differently in normal mode and show-ahead mode.

Ensure that the following conditions are met:

  • Do not assert the rdreq signal when the empty port is high. Enable the underflow protection circuitry or set the UNDERFLOW_CHECKING parameter to ON so that the FIFO can automatically disable the rdreq signal when it is empty.
  • The rdreq signal must meet the functional timing requirement based on the empty signal.
sclr/aclr Input No Assert this signal to clear all the output status ports, but the effect on the q output may vary for different FIFO configurations.
q Output Yes Shows the data read from the read request operation.

The width of the q port must be equal to the width of the data port. The port width is equal to the DATA_WIDTH parameter.

full

Output No

When asserted, the FIFO is considered full. Do not perform write request operation when the FIFO is full.

empty

Output No

When asserted, the FIFO is considered empty. Do not perform read request operation when the FIFO is empty.

almost_full Output No

Asserted when the usedw signal is greater than or equal to the ALMOST_FULL_VALUE parameter. It is used as an early indication of the full signal.

almost_empty Output No

Asserted when the usedw signal is lesser than the ALMOST_EMPTY_VALUE parameter. It is used as an early indication of the empty signal.

usedw

Output No Show the number of words stored in the FIFO.

Port width must be equal to the ADDR_WIDTH parameter.

byteena Input Yes

Byte enable port at Port A to masks the data_a port so that only specific bits of data are written to the memory.

This port is enabled in FIFO because the simple RAM supports data with BYTE_SIZE.

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