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1. Intel Agilex® 7 M-Series General-Purpose I/O Overview
2. Intel Agilex® 7 M-Series GPIO-B Banks
3. Intel Agilex® 7 M-Series HPS I/O Banks
4. Intel Agilex® 7 M-Series SDM I/O Banks
5. Intel Agilex® 7 M-Series I/O Troubleshooting Guidelines
6. GPIO Intel® FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Intel Agilex® 7 General-Purpose I/O User Guide: M-Series
9. Document Revision History for the Intel Agilex® 7 General-Purpose I/O User Guide: M-Series
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. VREF Sources and Input Standards Grouping
2.5.3. GPIO-B Pin Restrictions for External Memory Interfaces
2.5.4. RZQ Pin Requirement
2.5.5. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.6. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.7. Simultaneous Switching Noise
2.5.8. HPS Shared I/O Requirements
2.5.9. Clocking Requirements
2.5.10. SDM Shared I/O Requirements
2.5.11. Unused Pins
2.5.12. Voltage Setting for Unused GPIO-B Banks
2.5.13. GPIO-B Pins During Power Sequencing
2.5.14. Drive Strength Requirement for GPIO-B Input Pins
2.5.15. Maximum DC Current Restrictions
2.5.16. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.17. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.18. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.19. Implementing a Pseudo Open Drain
2.5.20. Allowed Duration for Using RT OCT
2.5.21. Single-Ended Strobe Signal Differential Pin Pair Restriction
6.1. Release Information for GPIO Intel® FPGA IP
6.2. Generating the GPIO Intel® FPGA IP
6.3. GPIO Intel® FPGA IP Parameter Settings
6.4. GPIO Intel® FPGA IP Interface Signals
6.5. GPIO Intel® FPGA IP Architecture
6.6. Verifying Resource Utilization and Design Performance
6.7. GPIO Intel® FPGA IP Timing
6.8. GPIO Intel® FPGA IP Design Examples
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2.4.1.1. Single-Ended I/O Standard OCT Termination
Serial (RS) and parallel (RT) OCT provides I/O impedance matching and termination capabilities.
The OCT calibration circuit uses the impedance of the external resistor that is connected to the RZQ pin as reference. During calibration, the circuit continuously alters the impedance of the I/O buffer until the impedance reaches a predetermined ratio to the reference resistance.
The OCT with calibration feature is not supported in GPIO mode.
Direction | OCT Scheme |
---|---|
Output | RS OCT with calibration |
RS OCT without calibration | |
Input | RT OCT with calibration |
RT OCT without calibration | |
Bidirectional | Dynamic RS and RT OCT |