Intel® FPGA AI Suite: SoC Design Example User Guide

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ID 768979
Date 12/01/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite SoC Design Example User Guide 2. About the SoC Design Example 3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial 4. Intel® FPGA AI Suite SoC Design Example Run Process 5. Intel® FPGA AI Suite SoC Design Example Build Process 6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture 7. Intel® FPGA AI Suite Soc Design Example Software Components 8. Streaming-to-Memory (S2M) Streaming Demonstration A. Intel® FPGA AI Suite SoC Design Example User Guide Archives B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History
2. About the SoC Design Example x
2.1. Intel® FPGA AI Suite SoC Design Example Prerequisites
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial x
3.1. Initial Setup 3.2. Initializing a Work Directory 3.3. (Optional) Create an SD Card Image (.wic) 3.4. Writing the SD Card Image (.wic) to an SD Card 3.5. Preparing the Intel® Arria® 10 SX SoC FPGA Development Kit for the Intel® FPGA AI Suite SoC Design Example 3.6. Adding Compiled Graphs (AOT files) to the SD Card 3.7. Running the Demonstration Applications
3.3. (Optional) Create an SD Card Image (.wic) x
3.3.1. Installing Prerequisite Software for Building an SD Card Image 3.3.2. Building the FPGA Bitstreams 3.3.3. Installing HPS Disk Image Build Prerequisites 3.3.4. (Optional) Downloading the ImageNet Categories 3.3.5. Building the SD Card Image
3.5. Preparing the Intel® Arria® 10 SX SoC FPGA Development Kit for the Intel® FPGA AI Suite SoC Design Example x
3.5.1. Confirming Intel® Arria® 10 SX SoC FPGA Development Kit Board Settings 3.5.2. Connect the Intel® Arria® 10 SX SoC FPGA Development Kit to the Host Development System 3.5.3. Configuring the Intel® Arria® 10 SX SoC FPGA Development Kit UART Connection 3.5.4. Determining the Intel® Arria® 10 SX SoC FPGA Development Kit IP Address
3.6. Adding Compiled Graphs (AOT files) to the SD Card x
3.6.1. Preparing OpenVINO™ Model Zoo 3.6.2. Preparing a Model 3.6.3. Compiling the Graphs 3.6.4. Copying the Compiled Graphs to the SD card
3.7. Running the Demonstration Applications x
3.7.1. Running the M2M Mode Demonstration Application 3.7.2. Running the S2M Mode Demonstration Application 3.7.3. Troubleshooting the Demonstration Applications
4. Intel® FPGA AI Suite SoC Design Example Run Process x
4.1. Exporting Trained Graphs from Source Frameworks 4.2. Compiling Exported Graphs Through the Intel® FPGA AI Suite
5. Intel® FPGA AI Suite SoC Design Example Build Process x
5.1. Building the Intel® Quartus® Prime Project 5.2. Building the Bootable SD Card Image (.wic)
5.1. Building the Intel® Quartus® Prime Project x
5.1.1. Intel® Quartus® Prime Build Flow 5.1.2. Build Script Options 5.1.3. Build Directory
5.1.1. Intel® Quartus® Prime Build Flow x
5.1.1.1. Build Synchronization of FPGA with Software
5.1.3. Build Directory x
5.1.3.1. The create_project.bash Script 5.1.3.2. The generate_sof.bash Script 5.1.3.3. The generate_rbf.bash Script 5.1.3.4. The build_stream_controller.sh Script
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture x
6.1. Intel® FPGA AI Suite SoC Design Example Inference Sequence Overview 6.2. Memory-to-Memory (M2M) Variant Design 6.3. Streaming-to-Memory (S2M) Variant Design 6.4. Top Level 6.5. The SoC Design Example Platform Designer System 6.6. Fabric EMIF Design Component 6.7. PLL Configuration
6.2. Memory-to-Memory (M2M) Variant Design x
6.2.1. The mSGDMA Intel FPGA IP 6.2.2. RAM considerations
6.3. Streaming-to-Memory (S2M) Variant Design x
6.3.1. Streaming Enablement for Intel® FPGA AI Suite 6.3.2. Nios® V Subsystem 6.3.3. Streaming System Operation 6.3.4. Resolving Input Rate Mismatches Between the Intel® FPGA AI Suite IP and the Streaming Input 6.3.5. The Layout Transform IP as an Application-Specific Block
6.3.3. Streaming System Operation x
6.3.3.1. Streaming System Buffer Management 6.3.3.2. Streaming System Inference Job Management
6.3.5. The Layout Transform IP as an Application-Specific Block x
6.3.5.1. Layout Transform Considerations 6.3.5.2. Layout Transform IP Register Map 6.3.5.3. Layout Transform Configuration Options
6.4. Top Level x
6.4.1. Clock Domains
6.5. The SoC Design Example Platform Designer System x
6.5.1. The dla_0 Platform Designer Layer (dla.qsys) 6.5.2. The hps_0 Platform Designer Layer (hps.qys)
7. Intel® FPGA AI Suite Soc Design Example Software Components x
7.1. Yocto Build and Runtime Linux Environment 7.2. Intel® FPGA AI Suite Runtime Plugin 7.3. Runtime Interaction with the MMD Layer 7.4. MMD Layer Hardware Interaction Library
7.1. Yocto Build and Runtime Linux Environment x
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb 7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend 7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb 7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb 7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend 7.1.6. Yocto Recipe: wic
7.4. MMD Layer Hardware Interaction Library x
7.4.1. MMD Layer Hardware Interaction Library Class mmd_device 7.4.2. MMD Layer Hardware Interaction Library Class uio_device 7.4.3. MMD Layer Hardware Interaction Library Class dma_device
8. Streaming-to-Memory (S2M) Streaming Demonstration x
8.1. Nios® Subsystem 8.2. Building the Stream Controller Module 8.3. Building the Streaming Demonstration Applications 8.4. Running the Streaming Demonstration
8.1. Nios® Subsystem x
8.1.1. Stream Controller Communication Protocol 8.1.2. Buffer Flow in Streaming Mode using Nios® V Software Scheduler
8.1.2. Buffer Flow in Streaming Mode using Nios® V Software Scheduler x
8.1.2.1. Review of M2M mode 8.1.2.2. External Streaming Mode Buffer Flow 8.1.2.3. Nios® V Stream Controller State Machine Buffer Flow
8.4. Running the Streaming Demonstration x
8.4.1. The streaming_inference_app Application 8.4.2. The image_streaming_app Application
1. Intel® FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial
4. Intel® FPGA AI Suite SoC Design Example Run Process
5. Intel® FPGA AI Suite SoC Design Example Build Process
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture
7. Intel® FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. Intel® FPGA AI Suite SoC Design Example User Guide Archives
B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History

5.2. Building the Bootable SD Card Image (.wic)

To create a bootable SD Card image (.wic file), the following components must be built:
  • Yocto Image
  • Yocto SDK Toolchain
  • Arm Cross-Compiled OpenVINO
  • Arm Cross-Compiled Intel® FPGA AI Suite Runtime Plugin
  • Arm Cross-Compiled Demonstration Applications
  • FPGA .sof/.rbf files

The create_hps_image.sh script performs the complete build process and combines all the necessary components into an SD card image that can be written to an SD card. For steps required to write an SD card image to an SD card, refer to Writing the SD Card Image (.wic) to an SD Card.

The SD card image is assembled using Yocto (https://yoctoproject.org).

You must have a build system that meets the minimum build requirements. For details, refer to https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The commands to install the required packages are shown in Installing HPS Disk Image Build Prerequisites.

To perform the build, run the following commands: 
cd $COREDLA_WORK\runtime
./create_hps_image.sh \
   -f <bitstream_directory> \
   -o <output_directory> \
   -u \
   -m arria10
The create_hps_image.sh script performs the following steps:
  1. Build the Yocto boot SD card image and Yocto SDK toolchain
  2. Build the HPS Packages
  3. Build the runtime
  4. Update the SD card image
The following diagram illustrates the overall build process performed by the create_hps_image.sh script:
Figure 2.  Intel® FPGA AI Suite SoC Design Example Build Process

Build the Yocto boot SD card image and Yocto SDK toolchain

The Intel® FPGA AI Suite Soc design example uses the Yocto Project Poky Distribution.

The Yocto image is based on the Intel® Arria® 10 Golden System Reference Designs, which you can find at the following URL: https://www.rocketboards.org/foswiki/Documentation/GSRD.

To customize the Yocto Poky distribution, modify the recipes found in layer $COREDLA_ROOT/hps/ed4/yocto/meta-intel-coredla.

More details can be found in Yocto Build and Runtime Linux Environment.

The defined Yocto Image recipe is coredla-image and can be found in $COREDLA_ROOT/hps/ed4/yocto/meta-intel-coredla/recipes-image/coredla-image.bb.

A Yocto SDK is also built as part of the build and this SDK is used in subsequent build steps to cross-compile the software for the Arm HPS subsystem:
  • Intel® Arria® 10 :

    $COREDLA_WORK/runtime/build_Yocto/build/tmp/deploy/sdk/poky-glibc-x86_64-lbs-image-poky-cortexa9t2hf-neon-arria10-toolchain-4.1.2.sh

The SD card image (WIC file) is in the following location:
  • Intel® Arria® 10 :

    $COREDLA_WORK/runtime/build_Yocto/build/tmp/deploy/images/arria10/*

By default, the create_hps_image.sh script builds Yocto from scratch. However, if a prebuilt Yocto build folder is available, you can specify the prebuilt Yocto folder via the -y option as follows: 
./create_hps_image.sh \
   -y <PREBUILT_YOCTO_DIR> 
   -f <BITSTREAM_DIR> \
   -o <OUTPUT_DIR> 
   -u
   -m arria10

This -y option loads the Yocto SDK from <PREBUILT_YOCTO_DIR>/build/tmp/deploy/sdk/ and the .wic image from <PREBUILT_YOCTO_DIR>/build/tmp/deploy/images/arria10/ without rerunning a Yocto build.

Build the HPS Packages

The HPS packages are built by the build_hpspackages.sh script.

This script cross-compiles OpenCV, OpenVINO, and the Arm-based OpenVINO™ runtime plugin.

Build the runtime

The runtimes are built by the build_runtime.sh script.

This script cross-compiles the OpenVINO™ Intel® FPGA AI Suite runtime plugin and demonstration applications for the SoC devices.

Update the SD card image

The SD card image is updated by the update_sd_image.sh script.

This script takes the output products from the previous build steps and builds a bootable SD Card image.

The software binaries are installed to the Ext4 partition under the /home/root/app directory. The RTL fit_spl_fpga.itb file is copied to the Fat32 partition.

The SD card image is updated only if you specify the -u option of the create_hps_image.sh command along with the location of the FPGA bitstream directory through the -f option.

You can skip updating the SD card while building the rest of the SoC Example Design by omitting the -f and -u options: 
./create_hps_image.sh \
   -o <OUTPUT_DIR> \
   -m arria10
When you skip updating the SD card image, you can build bitstreams and an HPS image (Yocto, HPS packages, Intel® FPGA AI Suite runtime) concurrently. You can update the SD card image (.wic file) image after all the files are ready: 
./create_hps_image.sh \
   -y ./build_Yocto
   -f <BITSTREAM_DIR> \
   -o <OUTPUT_DIR> \
   -u \
   -m arria10
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