FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 12/16/2024
Public
Document Table of Contents

6.1. Build Script

While this design example includes prepackaged bitstreams, you can also use the build script to build bitstreams.

To build the PCIe-based example design, use the bin/dla_build_example_design.py script. You can use this script to create an example design with one or multiple FPGA AI Suite IP instances.

The script generates a wrapper that wraps one or more IP instances along with adapters necessary to connect to the Terasic DE10-Agilex BSP.

When specifying an <architecture_file>, pay attention to the resource limitations on the FPGA, as well as the number of resources that the board support package (BSP) uses.

The dla_compiler tool includes a --fanalyze-area option to estimate the resources required for a single IP instance corresponding to an architecture file, as described in the FPGA AI Suite Compiler Reference Manual.

Implementing two instances (as is the default for dla_build_example_design.py) requires twice the resources.

Table 4.  Build Script Resources
Resources ALMs M20k DSPs
Resources available on Agilex™ 7 F-Series 014 device 487200 7110 4510
Reasonable Target Utilization 80% 90% 90%
Usable Resources 390000 6399 4059

The DE10-Agilex design is only validated for use with Quartus® Prime Pro Edition Version 24.3. The Agilex™ 7 device has significantly more resources and can support up to four IP instances.