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1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Agilex™ 7 FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
5.1. Exporting Trained Graphs from Source Frameworks
5.2. Compiling Exported Graphs Through the FPGA AI Suite
5.3. Compiling the PCIe* -based Example Design
5.4. Programming the FPGA Device ( Agilex™ 7)
5.5. Performing Accelerated Inference with the dla_benchmark Application
5.6. Running the Ported OpenVINO™ Demonstration Applications
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7.2.1. PLL Adjustment
The design example build script adjusts the PLL driving the FPGA AI Suite IP clock based on the fMAX that the Quartus® Prime compiler achieves.
A fully rigorous production-quality flow would re-run timing analysis after the PLL adjustment to account for the small possibility that change in PLL frequency might cause a change in clock characteristics (for example, jitter) that cause a timing failure. A production design that shares the FPGA AI Suite IP clock with other system components might target a fixed frequency and skip PLL adjustment