FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 7/31/2024
Public
Document Table of Contents

2. About the PCIe* -based Design Example

The FPGA AI Suite PCIe* -based design example ( Agilex™ 7) demonstrates how the Intel® Distribution of OpenVINO™ toolkit and the FPGA AI Suite support the look-aside deep learning acceleration model.

The PCIe-based design example ( Agilex™ 7) is implemented with the following components:

  • FPGA AI Suite IP
  • Intel® Distribution of OpenVINO™ toolkit
  • Terasic* DE10-Agilex Development Board
  • Sample hardware and software systems that illustrate the use of these components

This design example includes pre-built FPGA bitstreams that correspond to pre-optimized architecture files. However, the design example build scripts let you choose from a variety of architecture files and build (or rebuild) your own bitstreams, provided that you have a license permitting bitstream generation.

This design is provided with the FPGA AI Suite as an example showing how to incorporate the IP into a design. This design is not intended for unaltered use in production scenarios. Any potential production application that uses portions of this example design must review them for both robustness and security.