Intel® FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 7/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1. Intel® FPGA AI Suite PCIe-based Design Example User Guide

Updated for:
Intel® FPGA AI Suite 2023.2

The Intel® FPGA AI Suite PCIe* -based Design Example User Guide describes the design and implementation for accelerating AI inference using the Intel® FPGA AI Suite, Intel® Distribution of OpenVINO™ Toolkit, and an Intel® PAC with Intel® Arria® 10 GX FPGA or a Terasic* DE10-Agilex Development Board

The following sections in this document describe the steps to build and execute the design:
The following sections in this document describe design decisions and architectural details about the design:

Use this document to help you understand how to create a PCIe example design with the targeted Intel® FPGA AI Suite architecture and number of instances and compiling the design for use with the Intel FPGA Basic Building Blocks (BBBs) system.

About the Intel® FPGA AI Suite Documentation Library

Documentation for the Intel® FPGA AI Suite is split across a few publications. Use the following table to find the publication that contains the Intel® FPGA AI Suite information that you are looking for:
Table 1.   Intel® FPGA AI Suite Documentation Library
Title and Description  
Release Notes

Provides late-breaking information about the Intel® FPGA AI Suite including new features, important bug fixes, and known issues.

Link
Getting Started Guide

Get up and running with the Intel® FPGA AI Suite by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel® FPGA AI Suite

Link
IP Reference Manual

Provides an overview of the Intel® FPGA AI Suite IP and the parameters you can set to customize it. This document also covers the Intel® FPGA AI Suite IP generation utility.

Link
Compiler Reference Manual

Describes the use modes of the graph compiler (dla_compiler). It also provides details about the compiler command options and the format of compilation inputs and outputs.

Link
PCIe-based Design Example User Guide

Describes the design and implementation for accelerating AI inference using the Intel® FPGA AI Suite, Intel® Distribution of OpenVINO™ Toolkit, and an Intel® PAC with Intel® Arria® 10 GX FPGA or a Terasic* DE10-Agilex Development Board.

Link
SoC-based Design Example User Guide

Describes the design and implementation for accelerating AI inference using the Intel® FPGA AI Suite, Intel® Distribution of OpenVINO™ Toolkit, and an Intel® Arria® 10 SX SoC FPGA Development Kit.

Link

Intel® Distribution of OpenVINO™ Toolkit Requirement

To use the Intel® FPGA AI Suite, you must be familiar with the Intel® Distribution of OpenVINO™ Toolkit.

Intel® FPGA AI Suite Version 2023.2 requires the Intel® Distribution of OpenVINO™ Toolkit Version 2022.3 LTS. For OpenVINO™ documentation, refer to the following URL:

https://docs.openvino.ai/2022.3/documentation.html