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Ixiasoft
2.5.2.1. Parameter Group: Global Parameters
2.5.2.2. Parameter Group: activation
2.5.2.3. Parameter Group: pe_array
2.5.2.4. Parameter Group: pool
2.5.2.5. Parameter Group: depthwise
2.5.2.6. Module: softmax
2.5.2.7. Parameter Group: dma
2.5.2.8. Parameter Group: xbar
2.5.2.9. Parameter Group: filter_scratchpad
2.5.2.10. Parameter Group: input_stream_interface
2.5.2.11. Parameter Group: output_stream_interface
2.5.2.12. Parameter Group: config_network
2.5.2.13. Parameter Group: layout_transform_params
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Ixiasoft
3.1. IP Generation Utility Execution Flows
The IP generation utility (dla_create_ip command) has the following flows:
- Creating an IP Directory (--flow create_ip)
Use this flow to create a new FPGA AI Suite IP library directory, generate an IP, and place it in the library.
- Adding an Architecture to an IP Directory (--flow add_arch)
Use this flow to generate an IP and place it in an existing FPGA AI Suite IP library directory.
- Listing Architectures in an IP Directory (--flow list)
Use this flow to list the IPs in an existing IP library directory.
- Removing an Architecture from an IP Directory (--flow remove_arch)
Use this flow to remove an IP from an existing IP library directory.
Creating an IP Directory
This flow is typically first flow that you use. It creates an FPGA AI Suite IP library directory and adds an architecture as follows:
- Creates the IP library directory and copies all contents from <ai_suite_root>/fpga/ip_template/ into the new directory. The copied folder (<ip_template>) contains some basic Tcl scripts and Platform Designer IP configurations.
- Creates a <ip_directory>/Verilog directory and copies over RTL files that are common to any generated FPGA AI Suite IP architecture.
These files are listed in static_files.tcl, which is used to ensure that other flows (the Platform Designer flow and design assembly flows outside Platform Designer) have access to the list of RTL source files.
- Creates the following directory for each architecture-family pair to add to the IP library:
<ip_directory>/Verilog/<architecture>_<family>
This location stores architecture-specific files.
- Invokes an internal utility to read the architecture description file (.arch).
Output files are architecture-specific and are copied to the <ip_directory>/Verilog/<architecture>_<family> directory.
- For the specific architecture, creates a generated_files.tcl file and a dla_ip.qsf file in the <ip_directory>/Verilog/<architecture>_<family> directory.
Adding an Architecture to an Existing IP Directory
This flow adds a new architecture to an existing IP library directory as follows:
- Creates a <ip_directory >/Verilog directory and copies over RTL files that are common to any generated FPGA AI Suite IP architecture.
These files are listed in static_files.tcl, which is used to ensure that other flows (the Platform Designer flow and design assembly flows outside Platform Designer) have access to the list of RTL source files.
- Creates the following directory for each architecture-family pair to add to the IP library:
<ip_directory>/Verilog/<architecture>_<family>
This location stores architecture-specific files.
- Invokes an internal utility to read the architecture description file (.arch).
Output files are architecture-specific and are copied to the <ip_directory>/Verilog/<architecture>_<family> directory.
- For the specific architecture, creates a generated_files.tcl file and a dla_ip.qsf file in the <ip_directory>/Verilog/<architecture>_<family> directory.
Listing Architectures in an IP Directory
This flow lists all available architectures in the IP library directory. The utility looks for all <architecture_family> folders and displays them.
Removing an Architecture from an IP Directory
This flow removes an architecture from an IP library directory. The utility looks for a <architecture_family> folder and removes it.