FPGA AI Suite: IP Reference Manual

ID 768974
Date 9/06/2024
Public
Document Table of Contents

2.6.2. AXI Interfaces

Name

Type

Description

DDR0 Initiator

AXI4

Initiator port for connecting to DDR memory

CSR Responder

AXI4-Lite

Exposes IP MMIO region

Interrupt Initiator

Interrupt Sender

Level sensitive interrupt