FPGA AI Suite: Compiler Reference Manual

Download PDF
ID 768972
Date 12/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area and Power of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analysis Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

4.1. Inputs (dla_compiler Command Options)

--network-file Option

Syntax
--network-file=<network_file> <network_file_2> ... <network_file_n>
Description
This option specifies the path to your OpenVINO™ network topology (.xml) file or files. You can specify multiple files with this option to allow for a multigraph flow.

The network weight file (.bin) associated with each network topology file must be in the same folder as the network topology file and must use the same graph name.

Example
--network-file_name=/user_path1/graph1.xml /user_path2/graph2.xml
Parsed As
(vector<string>)

--plugins-file Option

Syntax
--plugins-file=path_to_plugins.xml
Description

This option is intended for expert use only and is rarely needed. Incorrect use of this option can result in obscure error messages.

This option specifies the path to a custom plugins.xml file that initializes the InferenceEngine::Core with a custom plugins.xml file.

The plugins.xml file indicates the locations for your custom FPGA AI Suite .so files: libcoreDLAHeteroPlugin.so and libcoreDLAAotPlugin.so.

Example
--plugins-file=./bin/plugins.xml
Parsed As
(string)

--batch-size Option

Syntax
--batch-size="<batch_size> <batch_size_2> ... <batch_size_n>"
Description
This option overrides of the network specified batch size.

For multigraphs, you can specify a single batch size to use for all all graphs or you can specify a batch size for each graph.

When you specify multiple batch sizes, you must specify the batch sizes in the same order that you specified the network topology files in the --network-file option. If the number of batch sizes specified does not match the number of --network-file arguments, the default batch size from the --network-file option is used.

Example
--batch="size 16 32"
Parsed As
(vector<int>)

--bin-data Option

Syntax
--bin-data
Description
Forces graph to be compiled for binary data input, regardless of input tensor shape. Binary data is read as the input layer type.

Otherwise, graphs with 1- or 3-channel inputs are converted to U8 inputs and binary input files are discarded.

Parsed As
(bool)
Level Two Title