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Ixiasoft
2.1. System Architecture
2.2. Data Path Between Ethernet MAC and MACsec
2.3. Data Path Between MACsec and MCDMA
2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client)
2.5. Data Path Illustrations
2.6. Interrupts
2.7. Packet FIFO
2.8. AXI-ST Rate Controller
2.9. Error Handling
2.10. Top Level Signals
6.5.1.1. MACsec Reset Sequence
6.5.1.2. TX Configuration Sequence
6.5.1.3. RX Configuration Sequence
6.5.1.4. TX Rekeying Sequence
6.5.1.5. RX Rekeying Sequence
6.5.1.6. Cut Through/Store Forward Mode
6.5.1.7. User Single/Multi Port Settings
6.5.1.8. Encrypt/Decrypt Port
6.5.1.9. Port Priority
6.5.1.10. Interrupt Generation and Register
6.6.1. macsec_initilize
6.6.2. macsec_get_attributes
6.6.3. macsec_get_sa_attributes
6.6.4. macsec_set_attributes
6.6.5. macsec_set_sa_attributes
6.6.6. macsec_read_register
6.6.7. macsec_write_register
6.6.8. macsec_set_port_configuration
6.6.9. macsec_rate_configuration
6.6.10. macsec_single_or_multi_port
6.6.11. macsec_crypto_mode
6.6.12. macsec_port_priority
6.6.13. macsec_register_isr
7.1. Software Requirements
7.2. Obtaining the Reference Design
7.3. Reference Design Directory Structure
7.4. Simulation Command Arguments
7.5. Simulation Test Cases
7.6. Complete Simulation Command
7.7. Simulation Requirements
7.8. Running Non-UVM Simulation
7.9. Running UVM Simulation
7.10. Building, Installing, and Running the Software
7.11. Building the Hardware Design
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Ixiasoft
2.10. Top Level Signals
The table below lists the top level signals.
Signal | Direction | Width | Description |
---|---|---|---|
fpga_clk_100 | Input | 1 | Clock input for CSR access |
fpga_clk_156p25 | Input | 1 | 156.25 MHz for Ethernet HSSI refclk |
fpga_clk_100_pcie | Input | 1 | 100 MHz for PCIe refclk |
fpga_reset_n | Input | 1 | External reset input (pin_perst_n) |
Ethernet Interface | |||
p0_rx_serial | Input | 2 | Transceiver phy serial input data |
p0_tx_serial | Output | 2 | Transceiver phy serial output data |
p8_rx_serial | Input | 2 | Transceiver phy serial input data |
p8_tx_serial | Output | 2 | Transceiver phy serial output data |
qsfp_modsel | Output | 2 | QSFP mode selection |
qsfp_lowpwr | Output | 2 | QSFP low power signal |
qsfp_rstn | Output | 2 | QSFP reset pin |
PCIe Interface | |||
pcie_p0_rx_serial | Input | 16/8 | PCIe Transceiver phy serial input data |
pcie_p0_tx_serial | Output | 16/8 | PCIe Transceiver phy serial output data |