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Assign the correct pin assignment for PWRMGT_SCL and PWRMGT_SDA in the Quartus® Prime software. |
- Ensure the pin assignment for PWRMGT_SCL and PWRMGT_SDA are assigned correctly in the Quartus® Prime > Device > Device and Pin Options > Configuration > Configuration Pin Options.
- Incorrect pin assignment for these pins causes configuration error due to invalid PMBus interface connection on the hardware or board.
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Set the correct VID parameters in the Quartus® Prime software:
- Bus speed
- Slave device type
- Slave device address
- Voltage output format
- For direct mode—coefficient m, b, and R
- For linear mode—coefficient N
- Translated voltage value unit—mV or V
- Enable the PAGE command—If you are using the multi-slave device voltage regulator, specify the output channel correctly. Set the output channels to 0xFF on the registered slave device to respond to the Vout_Command.
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- Ensure the VID parameters are set correctly in the Quartus® Prime > Device > Device and Pin Options > Power Management and VID.
- Incorrect VID parameters cause configuration error due to PMBus interface communication error.
- The linear mode voltage regulators typically report voltage in "volts" while the direct mode voltage regulators typically report voltage in "millivolts". For more details, refer to the voltage regulator data sheet.
- Slave device address is specified in hexadecimal format in the Quartus® Prime software. Incorrect address setting will cause the slave device to receive not acknowledge (NACK) command by the PMBus master mode.
- The PAGE command provides the ability to configure, control, and monitor through one of the following physical address:
- Multiple outputs on one unit, or
- Multiple non-PMBus devices through a PMBus device to a non-PMBus device adapter or bridge.
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For the PMBus on-board connection:
- Connect the PWRMGT_SCL and PWRMGT_SDA pins to pull-up resistor.
- Bi-directional level shifter between the FPGA and the external voltage regulator.
- For the connection guidelines, refer to the respective Pin Connection Guidelines.
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- Connect the PWRMGT_SCL and PWRMGT_SDA pins to a 1.8 V pull-up resistor.
- Ensure level shifter is placed on board between the FPGA PWRMGT_SCL and PWRMGT_SDA pins and the external voltage regulator.
- In general, the PMBus operates with 3.3 V single-ended I/O standard. Due to the limitation on FPGA that supports only 1.8 V single-ended I/O standard, a 1.8 V – 3.3 V level shifter is required to transfer or receive data from the external voltage regulator.
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The external voltage regulator must be PMBus-compliance:
- Intel® recommends using the voltage regulator under the Intel® validated list.
- If you are unable to select one of the Intel® validated regulators, refer to the Voltage Regulator Compatibility Check with the Intel® Power Management Firmware table to check the compatibility your selected voltage regulator with the Intel® 's firmware.
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- Specified command is required to ensure the FPGA's SmartVID firmware is able to successfully communicate with the external voltage regulator.
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