AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

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ID 750856
Date 2/14/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Reference Design Requirements

Use of this reference design requires the following:

  • Installation of the Intel® Quartus® Prime Pro Edition version 23.4 with support for the Intel Agilex® 7 device family.
  • Connection to the Intel Agilex® 7 F-Series or M-Series FPGA development board on the bench.

  • Download of the design example available in the following location:

    https://github.com/intel/fpga-partial-reconfig

    To download the design example:

    1. Click Clone or download.
    2. Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
    3. Navigate to the appropriate subfolder to access the reference design.
      • tutorials/agilex7f_external_pr_configuration
      • tutorials/agilex7m_external_pr_configuration
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