AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

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Date 2/14/2024
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Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Partial Reconfiguration External Configuration Controller Intel FPGA IP

The Partial Reconfiguration External Configuration Controller is required to use configuration pins to stream PR data for PR operation. You must connect all of the top-level ports of the Partial Reconfiguration External Configuration Controller Intel FPGA IP to the pr_request pin to allow the handshaking of the host with the secure device manager (SDM) from the core. The SDM determines which types of configuration pins to use, according to your MSEL setting.
Figure 2.  Partial Reconfiguration External Configuration Controller Intel® FPGA IP


Table 1.   Partial Reconfiguration External Configuration Controller Parameter Settings

Parameter

Value

Description

Enable Busy Interface

Enable or Disable

Allows you to Enable or Disable the Busy interface, which asserts a signal to indicate that PR processing is in progress during external configuration. Default setting is Disable.
Table 2.   Partial Reconfiguration External Configuration Controller Ports
Port Name Width Direction Function
pr_request 1 Input Indicates that the PR process is ready to begin. The signal is a conduit not synchronous to any clock signal.
pr_error 2 Output Indicates a partial reconfiguration error.:
  • 2'b01—general PR error
  • 2'b11—incompatible bitstream error
These signals are conduits not synchronous to any clock source.
pr_done 1 Output Indicates that the PR process is complete. The signal is a conduit not synchronous to any clock signal.
start_addr 1 Input Specifies the start address of PR data in Active Serial Flash. You enable this signal by selecting either Avalon® -ST or Active Serial for the Enable Avalon-ST Pins or Active Serial Pins parameter. The signal is a conduit not synchronous to any clock signal.
reset 1 Input Active high, synchronous reset signal.
out_clk 1 Output Clock source that generates from an internal oscillator.
busy 1 Output

The IP asserts this signal to indicate PR data transfer in progress. You enable this signal by selecting Enable for the Enable busy interface parameter.

Level Two Title