Visible to Intel only — GUID: wfp1650264476728
Ixiasoft
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
Visible to Intel only — GUID: wfp1650264476728
Ixiasoft
7.3. Transceivers
The transceiver provides physical lane with the line rate of 25.78125 Gbps.
Signal |
Direction |
Description |
---|---|---|
tx_serial | Output | TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair. |
rx_serial | Input | RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair. |