F-Tile 25G Ethernet Intel® FPGA IP User Guide

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ID 750198
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile 25G Ethernet Intel FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive 10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the F-Tile 25G Ethernet Intel FPGA IP Core
4. F-Tile 25G Ethernet Intel FPGA IP Parameters x
4.1. Main Tab Options 4.2. Analog Parameter Tab Options
4.2. Analog Parameter Tab Options x
4.2.1. Analog Parameter Settings
5. Functional Description x
5.1. F-Tile 25G Ethernet Intel FPGA IP Core Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile 25G Ethernet Intel FPGA IP Core Functional Description x
5.1.1. F-Tile 25G Ethernet Intel FPGA IP TX MAC Datapath 5.1.2. 25 GbE TX PCS 5.1.3. F-Tile 25G Ethernet Intel FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 25 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile 25G Ethernet Intel FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames 5.1.6.3. Dynamic Reconfiguration QSF Settings
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Dynamic Reconfiguration Interface Signals 7.7. Miscellaneous Status and Debug Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. TX Statistics Registers 8.4.2. RX Statistics Registers
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide

7.6. Dynamic Reconfiguration Interface Signals

Table 19.  Dynamic Reconfiguration Interface Signals

Signal

Direction

Width

Description

i_cpu_clk Input 1 NIOS CPU Subsystem Clock.
The clock supports the following frequency range:
  • 100 to 250 MHz frequency when Enable ECC protection is disabled.
  • 100 to 200 MHz frequency when Enable ECC protection is enabled.
Note: For simulation, set this clock to 100 GHz.
reconfig_clk Input 1 250 MHz reconfiguration clock.
reconfig_reset Input 1 Reconfiguration reset.
i_dr_host_avmm_address Input 10 Address.
i_dr_host_avmm_read Input 1 Read request.
i_dr_host_avmm_write Input 1 Write request.
o_dr_host_avmm_readdata Output 32 Read data.
o_dr_host_avmm_readdata_valid Output 1 Read data valid.
i_dr_host_avmm_writedata Input 32 Write data.
o_dr_host_avmm_waitrequest Output 1 Wait request.
i_dr_new_c_applied_ack Input 1 Specifies the full handshake acknowledgment in response to o_dr_new_cfg_applied signal. The signal is active when set to 1.
o_dr_error_status Output 1 Specifies the overall dynamic reconfiguration SIP error status, including dynamically reconfigured Nios® firmware errors. This signal is active when set to 1.
o_dr_in_progress Output 1 Specifies that the dynamic reconfiguration is in progress. This signal is active when set to 1.
o_dr_new_cfg_applied Output 1

Specifies the new configuration settings to the external logic, including tile CSRs, mux selection, etc.

Once the signal is sampled active, the external logic returns an acknowledgment to complete a full handshake signaling. Since this is a hardware action, the signal must complete within nanosecond ranges.

Once this signal is active, the Nios® continues to monitor the acknowledgment before proceeding to the next process in the dynamic reconfiguration flow. After an acknowledgment is sampled, this signal becomes inactive and the Nios® proceeds to the next step. If an acknowledgment is not sampled at a prolong period of time and time-out is enabled, this signal also becomes inactive and the Nios® proceeds to the next step at time-out. A time-out error also is signaled in this case.

o_dr_curr_profile_id Output 15

Specifies the selected profile. The signal is only valid when o_dr_new_cfg_applied is 1.

You must decode the values to decide if the design is dynamically reconfigured.
Level Two Title