F-Tile 25G Ethernet Intel® FPGA IP User Guide

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ID 750198
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile 25G Ethernet Intel FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive 10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the F-Tile 25G Ethernet Intel FPGA IP Core
4. F-Tile 25G Ethernet Intel FPGA IP Parameters x
4.1. Main Tab Options 4.2. Analog Parameter Tab Options
4.2. Analog Parameter Tab Options x
4.2.1. Analog Parameter Settings
5. Functional Description x
5.1. F-Tile 25G Ethernet Intel FPGA IP Core Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile 25G Ethernet Intel FPGA IP Core Functional Description x
5.1.1. F-Tile 25G Ethernet Intel FPGA IP TX MAC Datapath 5.1.2. 25 GbE TX PCS 5.1.3. F-Tile 25G Ethernet Intel FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 25 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile 25G Ethernet Intel FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames 5.1.6.3. Dynamic Reconfiguration QSF Settings
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Dynamic Reconfiguration Interface Signals 7.7. Miscellaneous Status and Debug Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. TX Statistics Registers 8.4.2. RX Statistics Registers
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide

4.2.1. Analog Parameter Settings

Table 10.  Analog Parameter Settings
Parameter Range Default Settings Description
FGT TX EQ
FGT TXEQ Post Tap 1, 1.0 step size 0–19 0 Options for FGT TX EQ Post Tap 1, in 1.0 step size increments.
FGT TXEQ Main Tap 1, 1.0 step size 0–55 35 Options for FGT TX EQ Main Tap 1, in 1.0 step size increments.
FGT TXEQ Pre Tap 1, 1.0 step size 0–15 5 Options for FGT TX EQ Pre Tap 1, in 1.0 step size increments.
FGT TXEQ Post Tap 2, 1.0 step size 0–7 0 Options for FGT TX EQ Post Tap 2, in 1.0 step size increments.
FGT RX
Select FGT RX On-chip Termination
  • RX_ONCHIP_TERMINATION_R_1 (85 Ohms)
  • RX_ONCHIP_TERMINATION_R_2 (100 Ohms)
RX_ONCHIP_TERMINATION_R_1 (85 Ohms) Selects the FGT on-chip RX termination setting.
Enable FGT RX AC-Couple
  • ENABLE
  • DISABLE
ENABLE Enables the FGT RX AC coupling setting.
Enable FGT VSR MODE
  • VSR_MODE_DISABLE
  • VSR_MODE_LOW_LOSS
  • VSR_MODE_HIGH_LOSS
VSR_MODE_LOW_LOSS Enables the FGT VSR mode setting.
RXEQ VGA Gain 0–63 0 Specifies the RX EQ VGA Gain value. Only set if rx_adapt_mode = RX_ADAPT_MODE_STATIC_EQ
RXEQ High Frequency Boost 0–63 0 Specifies the RX EQ high frequency boost value. Only set if rx_adapt_mode = RX_ADAPT_MODE_STATIC_EQ
RXEQ DFE Data Tap1 0–63 0 Specifies the RX EQ DFE data tap 1 value. Only set if rx_adapt_mode = RX_ADAPT_MODE_STATIC_EQ
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