F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 7/08/2024
Public
Document Table of Contents

7.4. Transceiver Reconfiguration Signals

You access the Transceiver and Ethernet control and status registers of the Hard IP using the Transceiver and Ethernet reconfiguration interface respectively. Both interfaces are Avalon® memory-mapped interface.

The Avalon® memory-mapped interface implements a standard memory-mapped protocol. You can connect an Avalon® master to this bus to access the registers of the embedded Transceiver PHY IP core.

Table 16.  Transceiver Reconfiguration Interface Ports of the F-Tile Ethernet Hard IPAll interface signals are clocked by the reconfig_clk clock.
Port Name Direction Description
reconfig_clk Input Avalon® clock. The clock frequency is 100 MHz. All transceiver reconfiguration interface signals are synchronous to reconfig_clk .
reconfig_reset Input Resets the Avalon® memory-mapped interface and all the registers to which it provides access.
reconfig_write Input Write enable signal. Signal is active high.
reconfig_read Input Read enable signal. Signal is active high.
reconfig_address[17:0] Input

Address bus.

reconfig_writedata[31:0] Input A 32-bit data write bus. reconfig_address specifies the address.
reconfig_readdata[31:0] Output A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted.
reconfig_waitrequest Output Indicates the Avalon® memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted.
reconfig_readdatavalid Output Indicates that the reconfig_readdata signal is valid.
Table 17.  Ethernet Reconfiguration Interface Ports of the F-Tile Ethernet Hard IP
Port Name Direction Description
reconfig_eth_address[13:0] Input Address for the Ethernet control status registers.
reconfig_eth_read Input Read request signal for the Ethernet control status registers.
reconfig_eth_write Input Write request signal for the Ethernet control status registers.
reconfig_eth_readdata[31:0] Output Reads data from this port when the reconfig_eth_read signal is asserted.
reconfig_eth_writedata[31:0] Input Writes data to this port when the reconfig_eth_write signal is asserted.
reconfig_eth_waitrequest Output Indicates that the control and status interface is busy and unable to respond to read or write requests.
reconfig_eth_readdatavalid Output Indicates that the reconfig_eth_readdata signal is valid.