F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 7/08/2024
Public
Document Table of Contents

7.6. Dynamic Reconfiguration Interface Signals

Table 19.  Dynamic Reconfiguration Interface Signals

Signal

Direction

Width

Description

i_cpu_clk Input 1 NIOS CPU Subsystem Clock.
The clock supports the following frequency range:
  • 100 to 250 MHz frequency when Enable ECC protection is disabled.
  • 100 to 200 MHz frequency when Enable ECC protection is enabled.
Note: For simulation, set this clock to 100 GHz.
reconfig_clk Input 1 250 MHz reconfiguration clock.
reconfig_reset Input 1 Reconfiguration reset.
i_dr_host_avmm_address Input 10 Address.
i_dr_host_avmm_read Input 1 Read request.
i_dr_host_avmm_write Input 1 Write request.
o_dr_host_avmm_readdata Output 32 Read data.
o_dr_host_avmm_readdata_valid Output 1 Read data valid.
i_dr_host_avmm_writedata Input 32 Write data.
o_dr_host_avmm_waitrequest Output 1 Wait request.
i_dr_new_c_applied_ack Input 1 Specifies the full handshake acknowledgment in response to o_dr_new_cfg_applied signal. The signal is active when set to 1.
o_dr_error_status Output 1 Specifies the overall dynamic reconfiguration SIP error status, including dynamically reconfigured Nios® firmware errors. This signal is active when set to 1.
o_dr_in_progress Output 1 Specifies that the dynamic reconfiguration is in progress. This signal is active when set to 1.
o_dr_new_cfg_applied Output 1

Specifies the new configuration settings to the external logic, including tile CSRs, mux selection, etc.

Once the signal is sampled active, the external logic returns an acknowledgment to complete a full handshake signaling. Since this is a hardware action, the signal must complete within nanosecond ranges.

Once this signal is active, the Nios® continues to monitor the acknowledgment before proceeding to the next process in the dynamic reconfiguration flow. After an acknowledgment is sampled, this signal becomes inactive and the Nios® proceeds to the next step. If an acknowledgment is not sampled at a prolong period of time and time-out is enabled, this signal also becomes inactive and the Nios® proceeds to the next step at time-out. A time-out error also is signaled in this case.

o_dr_curr_profile_id Output 15

Specifies the selected profile. The signal is only valid when o_dr_new_cfg_applied is 1.

You must decode the values to decide if the design is dynamically reconfigured.