Visible to Intel only — GUID: nfl1662451159018
Ixiasoft
Visible to Intel only — GUID: nfl1662451159018
Ixiasoft
3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel® FPGA IP
The transceivers require a separately instantiated F-Tile Reference and System PLL Clocks to generate the transceiver and system PLL reference clock.
In your IP design, you must include an F-Tile Reference and System PLL Clocks Intel FPGA IP core to pass logic generation flow. The F-Tile Reference and System PLL Clocks Intel FPGA IP must always connect to a protocol based Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP cannot be compiled or simulated as a standalone IP. For more information on parameters and port list for F-Tile Reference and System PLL Clocks Intel FPGA IP core, refer to the F-Tile Architecture and PMA/FEC Direct PHY IP User Guide.
- Mode of System PLL: ETHERNET_FREQ_805_156
- FGT Refclk frequency: 156.25 MHz
For more information, refer to the F-Tile Ethernet Intel FPGA IP Hard IP User Guide.