Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 741330
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

2.7. Hardware Limitations

  • The design example supports only two ports that can be tested with FMC loopback. The pin assignments is based on the soft-CDR mode pin location limitations and loopback mapping.
  • There are 2 .sof files with 2 ports with FMC loopback. In both cases, there are 2 ports left unconnected. You need to manually edit the .qsf file to generate 2 .sof files.
  • To test the traffic in Port 2 & 3, swap the pin constraints in the generated .qsf file with Port 0 & 1. Generate the .sof file after swapping the pin constraints.
  • Although there are 16 LVDS pin pairs broken to FMC connector, you can only use 2 ports as the other ports are split between the top and bottom of bank 3B.
Level Two Title