Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 741330
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 22.1.0
  • Updated OPN number in the following topics:
    • Hardware and Software Requirements topic.
    • Generating the Design Example topic.
  • Updated Generating the Design Example topic with preset name.
  • Updated the following diagrams with clock frequencies:
    • Hardware Design Block Diagram—Multiport Triple-Speed Ethernet Intel FPGA IP Hardware Design Example diagram.
    • Block Diagram of the Design Example Multiport 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS with LVDS I/O Simulation Testbench diagram.
  • Updated the steps in Test Procedure topic.
  • Added a new Design Constraints topic.
2023.04.17 23.1 21.1.0
  • Removed note in Quick Start Guide topic.
  • Updated Example Design Tab in the Triple-Speed Ethernet Intel FPGA IP Parameter Editor figure.
  • Updated Compiling and Configuring the Design Example in Hardware topic to include steps to program hardware design example.
  • Update Features topic.
  • Removed note in Hardware and Software Requirements topic.
  • Added a new diagram: Hardware Design Block Diagram—Multiport Triple-Speed Ethernet Intel FPGA IP Hardware Design Example in Functional Description topic.
  • Added a new topic: Hardware Testing.
  • Updated Test Procedure topic.
  • Added a new topic: Interface Signals.
  • Added a new topic: Hardware Limitations.
  • Updated product family name to "Intel Agilex® 7".
2022.12.09 22.3 21.1.0 Initial release.
Level Two Title