F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 8/16/2024
Public
Document Table of Contents

7.1.6.1. Deterministic Latency Clock Signals

Table 74.  Deterministic Latency Clock Signals
Name I/O Width Description
i_dl_sampling_clk I 1 Sampling clock for deterministic latency logic. The default frequency value is 228.571429 MHz.